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CPLD Proto’s – Binary to 7-segment

Posted March 24, 2012 by Chris

“This project was an excuse to learn about Verilog and programmable parts (cpld, fpga). I chose this project because someone asked about it on Usenet, and the generic response was “use a ROM” – but to get a ROM wide enough would have been expensive, and wasteful – most ROMs these days have many inputs and 8 outputs, we want one with few inputs and many outputs – 8 (or more) in and 21 out. I suggested a $1 CPLD instead (turns out you need a $2 CPLD), then decided to actually make one to see if it would work.”

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