FPGA/CPLD ADC Interface

The Software
           There are actually two different VHDL modules used in this project. One is the straight A/D 8 bit value displayed on the LED Outputs. The second one is a cumulative view of the converted value:
    -A/D 8 bits to LEDs
    -Cumulative LED Output



           This first VHDL module does exactly what we initially set out to do. It pulses the A/D to start conversion, then it gets the 8-bits from the A/D and finally it displays that 8-bit value on the middle 8 LEDs for the user to see.

A/D 8 Bit value Displayed On LEDs

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
	--Define The Core Entity
ENTITY AD_CONVERTER IS
PORT(   
		--25.175 MHz Clock
		CLK		: IN STD_LOGIC;		
		--Analog To Digital Converter
		ADC_ENABLE  : OUT STD_LOGIC;
		ADC_INPUT	: IN STD_LOGIC_VECTOR(7 DOWNTO 0);		
		--Output Display
		LED_OUTPUT	: OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
end AD_CONVERTER;

ARCHITECTURE behavior of AD_CONVERTER IS
SIGNAL adc_value : STD_LOGIC_VECTOR(7 DOWNTO 0);		
BEGIN
PROCESS(CLK)
variable cnt: integer range 0 to 25175000;
BEGIN
IF(RISING_EDGE(CLK))THEN 		
	IF(cnt = 12000)THEN
		ADC_ENABLE <= '1';
	END IF;		
	IF(cnt = 24000)THEN
		ADC_ENABLE <= '0';
	END IF;
	IF(cnt = 25000)THEN
		LED_OUTPUT <= '1' & (ADC_INPUT XOR "11111111") & '1';	
		cnt := 0;
	END IF;
	cnt := cnt + 1;		
END IF;
END PROCESS;
END behavior;

           This second VHDL module will take a different approach and perform a primitive evaluation so that the LED output represents the magnitude of the converted analog voltage in a way that's much easier on the eyes.

Cumulative Display of Converted Analog Voltage

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY AD_CONVERTER IS
PORT(   
		--25.175 MHz Clock
		CLK		: IN STD_LOGIC;		
		--Analog To Digital Converter
		ADC_ENABLE  : OUT STD_LOGIC;
		ADC_INPUT	: IN STD_LOGIC_VECTOR(7 DOWNTO 0);		
		--Output Display
		LED_OUTPUT	: OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
end AD_CONVERTER;
ARCHITECTURE behavior of AD_CONVERTER IS
SIGNAL adc_value : STD_LOGIC_VECTOR(7 DOWNTO 0);			
BEGIN
PROCESS(CLK)
variable cnt: integer range 0 to 25175000;
BEGIN
IF(RISING_EDGE(CLK))THEN
	IF(ADC_INPUT <= 25)THEN
		LED_OUTPUT <= "1111111110";
	ELSIF(ADC_INPUT > 25  AND ADC_INPUT < 50 )THEN
		LED_OUTPUT <= "1111111100";
	ELSIF(ADC_INPUT > 50  AND ADC_INPUT < 75 )THEN
		LED_OUTPUT <= "1111111000";
	ELSIF(ADC_INPUT > 75  AND ADC_INPUT < 100)THEN
		LED_OUTPUT <= "1111110000";
	ELSIF(ADC_INPUT > 100 AND ADC_INPUT < 125)THEN
		LED_OUTPUT <= "1111100000";
	ELSIF(ADC_INPUT > 125 AND ADC_INPUT < 150)THEN
		LED_OUTPUT <= "1111000000";
	ELSIF(ADC_INPUT > 150 AND ADC_INPUT < 175)THEN
		LED_OUTPUT <= "1110000000";
	ELSIF(ADC_INPUT > 175 AND ADC_INPUT < 200)THEN
		LED_OUTPUT <= "1100000000";
	ELSIF(ADC_INPUT > 200 AND ADC_INPUT < 225)THEN
		LED_OUTPUT <= "1000000000";
	ELSIF(ADC_INPUT > 225)THEN
		LED_OUTPUT <= "0000000000";
	END IF;
		
	IF(cnt = 12000)THEN
		ADC_ENABLE <= '1';
	END IF;
	
	IF(cnt = 24000)THEN
		ADC_ENABLE <= '0';
	END IF;
	
	IF(cnt = 25000)THEN
		cnt := 0;
	END IF;
	
	cnt := cnt + 1;		
END IF;
END PROCESS;
END behavior;

           So after all that work and staring at code, let's take a look at how the system actually works, time to take some data!