Course 5: FPGA and CPLD » Lesson 10: VHDL vs Verilog vs Schematic

Lesson 1

Introduction to FPGA and CPLD

Lesson 2

Hardware Hello World

Lesson 3

Input and Output

Lesson 4

Combinatorial Logic

Lesson 5

Procedural Logic

Lesson 6

Design a Binary Counter

Lesson 7

Parallel Hardware

Lesson 8

LED Dimming Via PWM

Lesson 9

Design a Handheld POV

Lesson 10

VHDL vs Verilog vs Schematic

Lesson Video

Lesson 10: VHDL vs Verilog vs Schematic

There are many ways to create a CPLD or FPGA image. The most common methods are with VHDL, Verilog or schematic capture. In this lesson we’ll explore and compare all three.

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