NTSC Video With VHDL

The Software
           Understanding the VHDL code is probably moderately difficult, so put your thinking cap on after you download the source code and start looking through it.
           The two main portions of the code that I want to introduce here are (1) the state machine design and (2) the data display output.

           Understanding where and how the data is output is key to understanding how to use this code. Second, understanding the state machine design used, will give you a better overall understanding of the key functions built into this VHDL module.

The State Machine

..
...
type lineState is (sFP,sHSYNC,sBP,sLINE);
type syncState is (sIMAGE,sVSYNC);
type vbiState is (sPRE,sVERT,sPOST,sBLANK);
type fieldState is (sEVEN,sODD);

signal line_State : lineState := sFP;
signal sync_State : syncState := sIMAGE;
signal field_State : fieldState := sEVEN;
signal vbi_State : vbiState;
...
..

           Four different overall states are used. Starting with the most obvious, fieldState. This tells you whether currently the Even or the Odd field is being output. The syncState state machine tells us whether we are currently in a vertical sync or data output state. The vbiState, shows all parts of the vertical sync and the lineState shows all the possible states when we are outputting each line of data.

           State machines are a great advantage of FPGAs and just by looking at these 8 lines of code we can get a feeling for how things will combine together later on in the actual hardware description in the VHDL.

Displaying Output Data

..
...
     when sLINE =>
          if (pixel < 263) then
          --3 Color Combo
               if pixel >= 0 and pixel < 80 then
                    --Output Black Color
                    composite_1v <= '1';
                    composite_0_5v <= '0';
                    composite_0_3v <= '0';
               elsif pixel >= 80 and pixel < 160 then
                    --Output White Color
                    composite_1v <= '0';
                    composite_0_5v <= '1';
                    composite_0_3v <= '0';
               elsif pixel >= 160 and pixel < 263 then
                    --Output Black Color
                    composite_1v <= '1';
                    composite_0_5v <= '0';
                    composite_0_3v <= '0';
               end if;
...
..

           Since each horizontal line has 263 visible pixels, if we want to show 3 color bars on the screen, it's as simple as splitting the screen into 3 regions as the VHDL above does. Notice the compositive_0_3v signal is never used, this signal is reserved for horizontal/vertical sync only. The 1v and 0.5v signals are used for the data display only. If we wanted to switch the lines to be horizontal instead of vertical, we would use the VHDL signal called line instead of pixel.
           The Chess Board project available for download above, shows you how to manipulate line/pixel output so that you can control every single pixel on the screen and not just 'regions'. Download it and take a look at the source code for yourself.