Project Info
Author: Chris
Difficulty: Medium
Time Invested: 2 Hours
Prerequisites:
Take a look at the above
tutorials before continuing
to read this tutorial.
Author: Chris
Difficulty: Medium
Time Invested: 2 Hours
Prerequisites:
Take a look at the above
tutorials before continuing
to read this tutorial.
For this tutorial the CPLD development board that was built previously will be used (seen in the CPLD Dev Board & An Introduction To Verilog tutorials). The altera UP1/UP2 development boards can be substituted if you haven't built the CPLD development board.
VHSIC - Very-High-Speed Integrated Circuits
The CPLD Development Board
Purpose & Overview of this project
The goal of this project is to learn the basics of the VHDL programming language. A small & short program will be created that displays output of the numbers 0->8 on the 7-segment display. The number to be displayed will depend upon the DIP switch input. If 0 is input, display 0..if 1, display 1..etc.