An Introduction To VHDL:

Data & Observations
           So program the CPLD with the project/program seen on the previous page. The same video from the Verilog tutorial is used to demonstrate the results because the results are infact the same. We just used a different programming method to reach the result. It should look similar to what you see here:

           The program does what it should. If bit 1 is set then the 7-segment display shows 1. If bit 2 then 2 is displayed & so on and so forth up to 8. This is because there are only 8 dip switches, so naturally it is limited.