The Software
Since Quartus II projects have many, many files I went ahead and just put them all together in a zip file that you can download (to the right). The .pof file is all you really need to program the CPLD.
The VHDL Format
Verilog uses the Entity/Architecture combination. You can think of the Entity as the definition of the device and the Architecture the description of what the device should do and what should be output given certain inputs. Here is a simple example with a few I/O declarations:
The above program creates an entity with 8 inputs, 7 outputs, notice how its all declared as a single 'port' in the entity. Afterwards we say that the device has an architecture but as of now is a blank architecture. This would be the same as a 20-pin IC that does nothing. Why does it do nothing? Easy, we haven't designed any logic circuitry (the architecture) for it yet.
Logic (The Architecture) In VHDL
Now we'll explore how to create the actual logic circuitry (architecture), along with how some I/O works in VHDL. Let's take a look at the complete program:
The new modification is a standard case (switch) statement. Since the switch statement uses inputs and outputs from the PORT declaration this architecture executes forever. The way it works is, the 8-bit input from the Dip_Switches input. Then the input is evaluated through the case/switch statement. If a match is found, then the led output is given the corresponding value. If no match is found, the default case is used. Enough talk, let's program it!
Since Quartus II projects have many, many files I went ahead and just put them all together in a zip file that you can download (to the right). The .pof file is all you really need to program the CPLD.
The VHDL Format
Verilog uses the Entity/Architecture combination. You can think of the Entity as the definition of the device and the Architecture the description of what the device should do and what should be output given certain inputs. Here is a simple example with a few I/O declarations:
-------« Begin Code »-------
--VHDL_Intro.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--First Define What I/O Ports The Device Will Have:
ENTITY VHDL_Intro IS
PORT (
Dip_Switch_Input : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
LED_Output : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END VHDL_Intro;
--Now Define The Architecture Of The Device
ARCHITECTURE behavior OF VHDL_Intro IS
BEGIN
END behavior;
-------« End Code »-------
The above program creates an entity with 8 inputs, 7 outputs, notice how its all declared as a single 'port' in the entity. Afterwards we say that the device has an architecture but as of now is a blank architecture. This would be the same as a 20-pin IC that does nothing. Why does it do nothing? Easy, we haven't designed any logic circuitry (the architecture) for it yet.
Logic (The Architecture) In VHDL
Now we'll explore how to create the actual logic circuitry (architecture), along with how some I/O works in VHDL. Let's take a look at the complete program:
-------« Begin Code »-------
--VHDL_Intro.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--First Define What I/O Ports The Device Will Have:
ENTITY VHDL_Intro IS
PORT (
Dip_Switch_Input : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
LED_Output : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END VHDL_Intro;
--Now Define The Architecture Of The Device
ARCHITECTURE behavior OF VHDL_Intro IS
BEGIN
WITH Dip_Switch_Input SELECT
LED_Output <=
"1111110" WHEN "00000000";
"0110000" WHEN "00000001";
"1101101" WHEN "00000010";
"1111001" WHEN "00000100";
"0110011" WHEN "00001000";
"1011011" WHEN "00010000";
"1011111" WHEN "00100000";
"1110000" WHEN "01000000";
"1111111" WHEN "10000000";
"0000000" WHEN OTHERS;
END behavior;
-------« End Code »-------
The new modification is a standard case (switch) statement. Since the switch statement uses inputs and outputs from the PORT declaration this architecture executes forever. The way it works is, the 8-bit input from the Dip_Switches input. Then the input is evaluated through the case/switch statement. If a match is found, then the led output is given the corresponding value. If no match is found, the default case is used. Enough talk, let's program it!