Current Part:

MAX 7128SLC84-10
84 Pin PLCC Socket
7805 +5v Regulator
3x 510Ω Resistors
3x 1kΩ Resistors
3x 2kΩ Trimpot
47uF Capacitor
4x 0.1uF Capacitor
25.175 MHz Canned Oscillator
VGA Connector
10 Pin Shrouded Header
30 Pin Sips
Prototype Board
Wirewrap Tool
Wirewrap Wire
ByteBlaster MV

Parts List Details
           You may or may not be familiar with the parts above so a picture of each item has been included to help give you an idea of what they look like. I'll go through and explain each part briefly below.

MAX 7128SLC84-10
           This is the CPLD used as a VGA controller for this tutorial. It has 128 macrocells and 2,500 usable logic gates. Believe it or not this is actually relatively small when compared to state of the art FPGA/CPLD's but for this tutorial it's more than enough.

7805 +5v Regulator
           This is the +5v regulator used to keep the voltages to the CPLD Vdd in check. The CPLD is power hungry so expect the regulator to get a little warm if you leave the system running for a while.

25.175 MHz Crystal
           Each resolution of VGA has a correlating 'perfect frequency' that matches the timing for each pixel. For 640x480 that frequency is 25.175 MHz, so don't think it's strange not to see a rounded number. If you like rounded numbers, switch to 800x600 which uses a 20 MHz clock, but finish this tutorial first!

510Ω, 1kΩ and 2kΩ
           These specific values should be used. If you're off by a few ohms, it's ok, but it will change the output color slightly. Try to get these values for the best results, the theory section will explain why they're so important.

10 Pin Shrouded Header
           This Altera style JTAG port will be used to program the CPLD through the ByteBlaster MV cable. It requires connecting to a few pins on the FPGA which we'll see in the schematic. Be sure to use this exact header as the ByteBlaster cable is made to connect perfectly with it.