DE0 Nano VGA Output

The Software
           Most people would hate to call VHDL or Verilog software, so let's settle with hardware description language. There's two main parts to the VHDL for this project.
    -VGA Synch Timing
    -8 State Machine Output

           The easier part is the 8-state machine output. The code below shows how the colors are chosen based off of a count value that counts up from zero to seven over and over.

8 State Machine Output

--Increment CNT Every Clock Cycle
IF(cnt = 50000000)THEN
   cnt := 0;
ELSE
   cnt := cnt + 1;
END IF;

--Increment Color Count Ever 1 Seconds
IF(cnt = 0)THEN
   color_cnt := color_cnt + 1;
END IF;

CASE color_cnt IS
   when 0 => --WHITE
      color_en <= "111";
   when 1 => --RED
      color_en <= "001";
   when 2 => --YELLOW
      color_en <= "011";
   when 3 => --GREEN
      color_en <= "010";
   when 4 => --TEAL
      color_en <= "110";
   when 5 => --BLUE
      color_en <= "100";
   when 6 => --VIOLET
      color_en <= "101";
   when 7 => --BLACK
      color_en <= "000";
   when others =>
      color_cnt := 0;
END CASE;

   --Generate Data For The Vertical Frame
IF (v_cnt >= 0) AND (v_cnt <= 799) THEN
   red_signal <= color_en(0);
   green_signal <= color_en(1);
   blue_signal <= color_en(2);
END IF;

           The second part of the VHDL code is the VGA timing synchronization. To meet the 72 Hz vertical refresh rate, a lot of specific changes needed to be made. The VHDL code seen below is basically a re-duplication of what I wrote for the Create VGA with VHDL tutorial. So, if you've already read and understood that tutorial, the VHDL below will seem straight forward.

Two Interrupt Service Routines

--Horizontal Sync
   --Generate Horizontal Sync
IF (h_cnt <= 975) AND (h_cnt >= 855) THEN
   h_sync <= '0';
ELSE
   h_sync <= '1';
END IF;

   --Reset Horizontal Counter
IF (h_cnt = 1039) THEN
   h_cnt <= "00000000000";
ELSE
   h_cnt <= h_cnt + 1;
END IF;

--Vertical Sync
   --Generate Vertical Sync
IF (v_cnt <= 642) AND (v_cnt >= 636) THEN
   v_sync <= '0';
ELSE
   v_sync <= '1';
END IF;

   --Reset Vertical Counter
IF (v_cnt >= 665) AND (h_cnt >= 1039) THEN
   v_cnt <= "00000000000";
ELSIF (h_cnt = 1039) THEN
   v_cnt <= v_cnt + 1;
END IF;

   --Generate Horizontal Data
IF (h_cnt <= 799) THEN
   horizontal_en <= '1';
ELSE
   horizontal_en <= '0';
END IF;

   --Generate Vertical Data
IF (v_cnt <= 599) THEN
   vertical_en <= '1';
ELSE
   vertical_en <= '0';
END IF;

--Assign Physical Signals To VGA
GPIO_1_D(1) <= red_signal AND video_en;
GPIO_1_D(3) <= green_signal AND video_en;
GPIO_1_D(5) <= blue_signal AND video_en;

GPIO_1_D(7) <= h_sync;
GPIO_1_D(9) <= v_sync;

           These two modules work together to form the exact same output as the Masochist's Video Card, with substantially less work. It's on the order of 1 hour developing VHDL and testing vs. 10 hours developing, wire-wrapping 74 series IC's and testing.