Since Quartus II projects have many, many files I went ahead and just put them all together in a zip file that you can download (to the right). The .pof file is all you really need to program the CPLD.
Combined 4-Bit Adder
One really nice feature of Quartus II is the RLT Viewer. Below you'll see a picture of the entire circuit that the VHDL code in Project_1 creates. The RTL viewer shows the circuit in the form of gate logic instead of just plain VHDL code.
Stage & Port
In the main vhdl program that puts everything together 4 stages are used, each stage uses a 1-bit adder port. The main vhdl program combines these to create The 4-bit adder. The architecture of the PORT can be seen just following the main Project_1 entity:
With the software complete, let's take a look at what happens when we load it onto the UP1 Board.