FPGA/CPLD 16x2 LCD Interface

Schematic Overview
           The schematic for this project is a modified version of the CPLD dev board schematic. There are a few new parts added for this project and you can see the completed schematic for this project below. The main parts in the schematic are the CPLD Dev Board, 16x2 LCD (HD44780) and ByteBlasterMV.

EPM7128 CPLD + MAX233A Interface

View Full Schematic

Schematic Specifics

Power Regulator
           The power regulation circuit is a LM7805 +5v regulator that will convert the +9v from the battery to a steady +5v output to the CPLD.

16x2 LCD Connection
           The 16x2 LCD makes 11 digital I/O connections to the CPLD/FPGA when used in 8-bit mode (In 4-bit mode, only 7 connections are necessary). Since we're using 8-bit mode all of these connections are necessary. The rest of the LCD's pins are power connection and contrast from the 5kΩ trimpot.

CPLD Dev Board
           This protoboard for a cpld was developed by me a few years ago. It's really just a PLCC CPLD in a socket with power and JTAG connectors for programming.

25.175 MHz Oscillator
           This oscillator was chosen mostly at random. We needed some type of timing device to keep a reference to time and I had this one laying around. Generally if you can find a clock above 10 MHz you'll be fine for this project.



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