VGA Hsync/Vsync Theory
The first problem with designing a VGA interface/video card using TTL logic chips is that most standard chips cannot exceed 25 MHz! This means we need to use a dividable frequency and hope we can still meet timing. So let's take a look at how we can use 10 MHz to meet the 800x600 standard.
VGA Hsync Timing @ 10 MHz
40 MHz is probably the only frequency in the VGA standard that can be easily divided. As you can see above we only have to divide everything by 4. So it turns out to be easy! We now know that at 10 MHz, a horizontal sync is necessary on pixels 210 -> 242 and that we can stop counting pixels at 264, because everything starts over.
VGA Vsync Timing @ 10 MHz
The vertical timing is more straight forward as no trickery is necessary. We only need to count every horizontal line that is output and when 601 - 605 are reached the Vsync signal should be triggered. Similarly, when the total of 628 is reached, the vertical system is finished and should restart counting from 0.
The first problem with designing a VGA interface/video card using TTL logic chips is that most standard chips cannot exceed 25 MHz! This means we need to use a dividable frequency and hope we can still meet timing. So let's take a look at how we can use 10 MHz to meet the 800x600 standard.
40 MHz is probably the only frequency in the VGA standard that can be easily divided. As you can see above we only have to divide everything by 4. So it turns out to be easy! We now know that at 10 MHz, a horizontal sync is necessary on pixels 210 -> 242 and that we can stop counting pixels at 264, because everything starts over.
The vertical timing is more straight forward as no trickery is necessary. We only need to count every horizontal line that is output and when 601 - 605 are reached the Vsync signal should be triggered. Similarly, when the total of 628 is reached, the vertical system is finished and should restart counting from 0.