Creating VGA With VHDL: Software

The Software
           The entire software project is included in the zip file for download. The main vhdl file (.vhd) is heavily commented to help you understand what is going on. The pin assignments are also already done as well.

What It Takes
           The software for this project is quite long so I'll only go over some of the more important parts. For the entity that we are creating in VHDL:

ENTITY VHDL_VGA IS
PORT(
     --Counter/VGA Timing
     clk     : IN STD_LOGIC;
     -VGA Signals/Pins
     hsync,
     vsync,
     red,
     green,
     blue     : OUT STD_LOGIC;
     --Sync Counters
     row,
     column     : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
end VHDL_VGA;

           As you can see in the entity we only need 5 outputs to the VGA connector to output a signal to the monitor. The one input we use will be a clock input from the 25.175MHz clock which is 'perfect' for 640x480 resolution & VHDL.

Specific Timing
           The following code will allow us to create the specific timing necessary for each signal:

WAIT UNTIL(clk'EVENT) AND (clk = '1');
     IF(cnt = 25175000) THEN
          cnt := 0;
     ELSE
          cnt := cnt + 1;
     END IF;

           The first line shows that we will always wait 1 clock cycle before performing the rest of the process. The rest of the code is not actually used in the problem but through the rest of the process cnt can be used as a reference for timing necessities.