A Simple VHDL Counter: Software

Program Download:

Quartus II Project Files
counter_slow.zip

The Software
           Since Quartus II projects have many, many files I went ahead and just put them all together in a zip file that you can download (to the right). The .pof file is all you really need to program the CPLD.

The 8-Bit Adder
           The counter is already a logic device that is well-reknowned. The idea and implementation have been around for decades, so creating one in VHDL is just a matter of clocking properly & incrementing. The core of the code that creates the basic counter is seen below:

-------« Begin Code »-------
if(clk'EVENT AND clk='1') THEN
     if(cnt = speed) THEN --Creates 1Hz Clock Divider
     cnt := 0;
          if(DIR='1') THEN --If Set As Up Counter Add
               O_buf <= O_buf+1;
          else --If Set As Down Counter Subtract
               O_buf <= O_buf-1;
          end if;
     else
          cnt := cnt+1; --Otherwise Increment Main Counter
     end if;
end if;

-------« End Code »-------

The Code Explained
           Many of these variables are defined before this actual code is seen in the program but their names define their purpose. The Speed is variable in this program thusly a variable is used instead of a static number for slowing the clocking. The UP2 board uses a 25.175MHz crystal clock input so initially we just make speed = 25,175,000. When the main counter reaches this value, effectively 1 second has gone by which is our desired result in terms of frequency.
           The rest of the code is really just filling in the blanks as well as pleasantries. Such as displaying the results on the LEDs and the 7-Segment displays. So, with the software complete, let's take a look at what happens when we load it onto the UP2 Board.



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