LCD_VGA_TEST Project Status (01/08/2010 - 09:16:20)
Project File: LCD_VGA_TEST.ise Implementation State: Programming File Generated
Module Name: main
  • Errors:
No Errors
Target Device: xc4vfx12-12ff668
  • Warnings:
25 Warnings
Product Version:ISE 11.1
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 64 10,944 1%  
Number of 4 input LUTs 82 10,944 1%  
Number of occupied Slices 71 5,472 1%  
    Number of Slices containing only related logic 71 71 100%  
    Number of Slices containing unrelated logic 0 71 0%  
Total Number of 4 input LUTs 130 10,944 1%  
    Number used as logic 82      
    Number used as a route-thru 48      
Number of bonded IOBs 24 320 7%  
    IOB Flip Flops 18      
Number of BUFG/BUFGCTRLs 1 32 3%  
    Number used as BUFGs 1      
Average Fanout of Non-Clock Nets 2.59      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Jan 8 09:15:00 2010024 Warnings10 Infos
Translation ReportCurrentFri Jan 8 09:15:10 2010000
Map ReportCurrentFri Jan 8 09:15:24 201001 Warning2 Infos
Place and Route ReportCurrentFri Jan 8 09:15:48 2010003 Infos
Power Report     
Post-PAR Static Timing ReportCurrentFri Jan 8 09:16:00 2010003 Infos
Bitgen ReportCurrentFri Jan 8 09:16:20 2010001 Info
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 01/08/2010 - 09:21:00