LCD_VGA_TEST Project Status (01/08/2010 - 08:48:05)
Project File:	LCD_VGA_TEST.ise	Implementation State:	Programming File Generated
Module Name:	main	Errors:	No Errors
Target Device:	xc4vfx12-12ff668	Warnings:	62 Warnings
Product Version:	ISE 11.1	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Setup: 0, Hold: 0) (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	85	10,944	1%
Number of 4 input LUTs	133	10,944	1%
Number of occupied Slices	106	5,472	1%
Number of Slices containing only related logic	106	106	100%
Number of Slices containing unrelated logic	0	106	0%
Total Number of 4 input LUTs	195	10,944	1%
Number used as logic	133
Number used as a route-thru	62
Number of bonded IOBs	24	320	7%
IOB Flip Flops	9
Number of BUFG/BUFGCTRLs	1	32	3%
Number used as BUFGs	1
Number of FIFO16/RAMB16s	18	36	50%
Number used as RAMB16s	18
Average Fanout of Non-Clock Nets	3.50

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Fri Jan 8 08:46:39 2010	0	61 Warnings	4 Infos
Translation Report	Current	Fri Jan 8 08:46:49 2010	0	0	0
Map Report	Current	Fri Jan 8 08:47:04 2010	0	1 Warning	2 Infos
Place and Route Report	Current	Fri Jan 8 08:47:29 2010	0	0	3 Infos
Power Report
Post-PAR Static Timing Report	Current	Fri Jan 8 08:47:42 2010	0	0	3 Infos
Bitgen Report	Current	Fri Jan 8 08:48:05 2010	0	0	1 Info

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 01/08/2010 - 08:48:05