NTSC Project Status (01/30/2010 - 12:18:53)
Project File:	NTSC.ise	Implementation State:	Programming File Generated
Module Name:	ntsc_TOP	Errors:	No Errors
Target Device:	xc4vfx12-12ff668	Warnings:	1 Warning
Product Version:	ISE 11.1	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Setup: 0, Hold: 0) (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	88	10,944	1%
Number of 4 input LUTs	338	10,944	3%
Number of occupied Slices	195	5,472	3%
Number of Slices containing only related logic	195	195	100%
Number of Slices containing unrelated logic	0	195	0%
Total Number of 4 input LUTs	377	10,944	3%
Number used as logic	338
Number used as a route-thru	39
Number of bonded IOBs	7	320	2%
Number of BUFG/BUFGCTRLs	1	32	3%
Number used as BUFGs	1
Average Fanout of Non-Clock Nets	3.51

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Sat Jan 30 12:17:21 2010	0	0	0
Translation Report	Current	Sat Jan 30 12:17:31 2010	0	0	0
Map Report	Current	Sat Jan 30 12:17:47 2010	0	1 Warning	2 Infos
Place and Route Report	Current	Sat Jan 30 12:18:17 2010	0	0	3 Infos
Power Report
Post-PAR Static Timing Report	Current	Sat Jan 30 12:18:30 2010	0	0	3 Infos
Bitgen Report	Current	Sat Jan 30 12:18:52 2010	0	0	1 Info

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 01/30/2010 - 12:18:53