#7 Parallel Hardware [Post Homework Here]

[ThePyroElectro]

A new lesson was posted today:
http://www.pyroelectro.com/edu/fpga/parallel_hardware/

Post your homework answers here to compare with everyone else!

[Bingo600]

Hi Chris

Here is my homework

What are some advantages of building CPLD hardware modules that operate in parallel?

The logic flows are independant (as in per process), that makes all processes flow execute simoultainously (parallel)
This capability enables us to get a FPGA/CPLD to act as if it were many individual external "logic chips".
One process per "chip".

HOMEWORK QUESTION 2
Create a new CPLD project and build two combinatorial logic statements that operate in
parallel: Y = (A + BC) , Z = (D + E + F). Show the RTL viewer output to prove they will be
parallel statements.

I had to be sure about the boolean expressions , and had to look up the operators + = "or" and * (or "Nothing") = "and"
http://www.doc.ic.ac.uk/~dfg/hardware/H ... ture01.pdf

I translate the requirements to be: A process where Y = (A or (B and C)) , and one where Z = (D or E or F)

This is my VHDL code.

Code: Select all

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lesson7a is
   port(
         A,B,C: in std_logic;
         Y:       out std_logic;
         D,E,F: in std_logic;
         Z:       out std_logic
   );
end lesson7a;

architecture rtl of lesson7a is
begin
   BLK_0 : process(A,B,C)
   begin
      Y <= (A or (B and C));
   end process BLK_0;
   
   BLK_1 : process(D,E,F)
   begin
      Z <= (D or E or F);
   end process BLK_1;
   
end rtl;


And the RTL Viever

slesson7a.png (24.75 KiB) Viewed 15527 times

HOMEWORK QUESTION 3
In lesson 7 we gave an example of bit-coin mining, where a CPLD/FPGA would out-perform a
processor. Can you think of another example?

Crypto key breaking
Polygon drawing/shading (Graphics)
HighSpeed Communication / Interfacing (PCI Bus etc).
LED Controlling (Flatpanels etc.)

/Bingo

[ThePyroElectro]

Hi Bingo,

Correct answers!

I would add two simple comments

[Question 1]

We can even control process flow so that they can either both be serial or parallel with other processes. Like for example if we first divide down a clock frequency with a process and then use that slower clock signal to run another process.

[Question 2]

This can be done either in combinatorial logic or in a process, so it is a bit of a trick question. Since you chose the process route, I'll make a note that when you look at the RTL viewer it's also giving you sequential timing information with the ~0 and ~1. I tried to find the PDF on Altera's website that explains this in further detail, but no luck

[Bingo600]

Hi Bingo,

Correct answers!

I would add two simple comments

[Question 1]

We can even control process flow so that they can either both be serial or parallel with other processes. Like for example if we first divide down a clock frequency with a process and then use that slower clock signal to run another process.


[Question 2]

This can be done either in combinatorial logic or in a process, so it is a bit of a trick question. Since you chose the process route, I'll make a note that when you look at the RTL viewer it's also giving you sequential timing information with the ~0 and ~1. I tried to find the PDF on Altera's website that explains this in further detail, but no luck

I did provide an implementation here of the lesson7 on the S3E board
viewtopic.php?f=26&t=832

I had hoped for a comment

/Bingo