## #4 Combinatorial Logic [Post Homework Here]

Talk about the fifth PyroEDU course here.
ThePyroElectro
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### #4 Combinatorial Logic [Post Homework Here]

A new lesson was posted today:
http://www.pyroelectro.com/edu/fpga/combinatorial_logic/

Post your homework answers here to compare with everyone else!

Bingo600
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### Re: #4 Combinatorial Logic [Post Homework Here]

Chris i'm in Sweden this weekend.
Will do the homework when i get home

/BIngo

ThePyroElectro
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### Re: #4 Combinatorial Logic [Post Homework Here]

Bingo600 wrote:Chris i'm in Sweden this weekend.
Will do the homework when i get home

/BIngo

No rush. Don't get stockholm syndrome .

Bingo600
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### Re: #4 Combinatorial Logic [Post Homework Here]

Hi Chris here is my homework for lesson4

HOMEWORK QUESTION 1
Name 5 combinatorial logic operators that you can use in VHDL.

AND,OR,XOR,NOT,NAND,NOR

HOMEWORK QUESTION 2
Is it possible to implement all of the logic in a 74_08 (Quad 2-input AND Gate) logic IC inside
of our EPM3032A CPLD? (please explain why yes/no).

Yes it is

Code: Select all

`library ieee;use ieee.std_logic_1164.all;entity lesson4_7408 isport(   --    -- Modelled after NXP 74F08    -- http://www.nxp.com/documents/data_sheet/74F08.pdf   --   D0a:    in std_logic;    D0b:    in std_logic;    Q0:      out std_logic;   --   D1a:    in std_logic;    D1b:    in std_logic;    Q1:      out std_logic;   --   D2a:    in std_logic;    D2b:    in std_logic;    Q2:      out std_logic;   --   D3a:    in std_logic;    D3b:    in std_logic;    Q3:      out std_logic);end lesson4_7408;architecture rtl of lesson4_7408 isbegin--Logic to implement a 74F08   Q0 <= D0a AND D0b;   Q1 <= D1a AND D1b;   Q2 <= D2a AND D2b;   Q3 <= D3a AND D3b;   end rtl;`

RTL Viewer
Screenshot-RTL Viewer - -home-cfo-x-altera-pyro-course-lesson4-7408-lesson4-7408 - lesson4-7408.png (52.51 KiB) Viewed 9830 times

HOMEWORK QUESTION 3
Pretend A,B,C,D and Y are std_logic signals. Translate
This logic diagram to VHDL combinatorial logic.

Code: Select all

`library ieee;use ieee.std_logic_1164.all;entity lesson4_q3 isport(   a:    in std_logic;    b:    in std_logic;    c:    in std_logic;    d:    in std_logic;    y:      out std_logic);end lesson4_q3;architecture rtl of lesson4_q3 isbegin--Logic to implement a lesson4 question 3   y <=  d NAND ((NOT c) or (a AND b));   end rtl;`

RTL Viewer
Screenshot-RTL Viewer - -home-cfo-x-altera-pyro-course-lesson4_q3-lesson4_q3 - lesson4_q3.png (44.71 KiB) Viewed 9830 times
Last edited by Bingo600 on Tue Jul 22, 2014 3:49 pm, edited 1 time in total.

Bingo600
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### Re: #4 Combinatorial Logic [Post Homework Here]

Question 3 was a tough one....
I had to grumble for a while
But just what i wanted to learn VHDL for.

I hope i got it correct , the RTL Viewer seems to inducate that i have.

Btw: I attacked the Logic "backwards , meaning the logic closest to the output was also written closest to the output assignment.

Does that matter ???

/Bingo

ThePyroElectro
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### Re: #4 Combinatorial Logic [Post Homework Here]

Bingo600 wrote:Hi Chris here is my homework for lesson4
...
...
...

All correct answers Bingo and admittedly more than I was expecting, well done! The RTL viewer is a very helpful feature as you seem to have already noticed.

Bingo600 wrote:Question 3 was a tough one....
I had to grumble for a while
But just what i wanted to learn VHDL for.

I hope i got it correct , the RTL Viewer seems to inducate that i have.

Btw: I attacked the Logic "backwards , meaning the logic closest to the output was also written closest to the output assignment.

Does that matter ???

/Bingo

Yes you answered question 3 correctly. With logic personally I tend to separate the levels out vertically and attack it input to output. But you can surely use this method from either side to build up the combinatorial logic statement.

Bingo600
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Posts: 75
Joined: Sat Jun 28, 2014 7:22 am

### Re: #4 Combinatorial Logic [Post Homework Here]

ThePyroElectro wrote: With logic personally I tend to separate the levels out vertically and attack it input to output. But you can surely use this method from either side to build up the combinatorial logic statement.

So the order doesn't matter : as in

y <= d NAND ((NOT c) or (a AND b));

and

y <= ((NOT c) or (a AND b)) NAND d;

Produces the same ?

I could try ,but i'd like a definitive ansver

/Bingo

ThePyroElectro
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Posts: 1181
Joined: Mon Nov 12, 2007 9:24 pm
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### Re: #4 Combinatorial Logic [Post Homework Here]

Bingo600 wrote:
ThePyroElectro wrote: With logic personally I tend to separate the levels out vertically and attack it input to output. But you can surely use this method from either side to build up the combinatorial logic statement.

So the order doesn't matter : as in

y <= d NAND ((NOT c) or (a AND b));

and

y <= ((NOT c) or (a AND b)) NAND d;

Produces the same ?

I could try ,but i'd like a definitive ansver

/Bingo

Hi Bingo,

I only briefly mentioned it in the video, but in this case the order of operations comes into play since we are using parenthesis, statements inside parenthesis will be given precedence and executed first.

So yes, the order won't matter. Both should work.

A quick link about VHDL operator precedence:
http://www.csee.umbc.edu/portal/help/VHDL/operator.html

Highest precedence first, left to right within same precedence group, use parenthesis to control order.

So if you look at the precedence table you could actually write the combinatorial expression without any parenthesis. However personally I find the parenthesis useful when reading through my old code.

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