#10 VHDL vs Verilog vs Schematic [Post Homework Here]

[ThePyroElectro]

A new lesson was posted today:
http://www.pyroelectro.com/edu/fpga/vhdl_verilog_schematic/

Post your homework answers here to compare with everyone else!

[Bingo600]

Chris i'm a bit late

But my vacation is finish , and i was hit hard at work.

Well here is my homework

HOMEWORK QUESTION 1
Which design methodology (Verilog / VHDL / Schematic) is best suited for a large scale
project? Why?

Code: Select all

1: Schematic entry is cumbersome to change if large changes has to be made.
   Consider a latch has to be changed from 16 to 32 bit's , that's a lot of wires to redraw.

2: This is where the HDL has it's advantages.
   But i will not go into a VHDL vs. Verilog war.
   Instictively i would go for Verilog because i have a C background.
   But i will continue to use VHDL , primarily because it forced me to drop the "C" (sequential) thinking.
   But also because VHDL seems to be the chosen language here in Europe.


HOMEWORK QUESTION 2
Use the schematic – block diagram design method to make a simple design of your choice.

Simple but time consuming


See attached zip

I have made a 1Hz blink led on my EPM240 board ,witch have a 50Mhz Clock
So i'll use 4 x HC390 dividers in a divide : 100 / 100 / 100 / 50 configuration.

It took a very long time compared with what i would have used in VHDL

It won't fit in the EPM3032 as it uses 39 Cells , but that's not a problem with my EPM240

Code: Select all

Flow Status   Successful - Thu Sep  4 19:54:19 2014
Quartus II 64-Bit Version   13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name   lesson10d
Top-level Entity Name   lesson10d
Family   MAX II
Device   EPM240T100C5
Timing Models   Final
Total logic elements   39 / 240 ( 16 % )
Total pins   3 / 80 ( 4 % )
Total virtual pins   0
UFM blocks   0 / 1 ( 0 % )


To small to really see , and the PDF is larger than 256k , so i can't upload a decent print of the schematic

lesson10d.png (149.14 KiB) Viewed 7393 times

HOMEWORK QUESTION 3
After getting a sneak peak at Verilog, VHDL and Schematic. Which method of building a
CPLD/FPGA image do you like the most? Why?

I like Verilog the most , but will use VHDL.
I will try not to use Schematic , as i need the VHDL training .....


Afterthought:

Well after havng tried the schematic for the 50.000.000 divider ,
i'm positive that i won't use the schematic for anything but
simple combinatoric logic. If i'll ever use it again.


Edit:
Btw. Why don't CPLD's have pullup/pulldown's like the FPGA's
I actually had to connect RESET to GND before my EPM240 would blink at 1Hz



/Bingo

[ThePyroElectro]

Chris i'm a bit late

But my vacation is finish , and i was hit hard at work.

Well here is my homework

HOMEWORK QUESTION 1
Which design methodology (Verilog / VHDL / Schematic) is best suited for a large scale
project? Why?

Code: Select all

1: Schematic entry is cumbersome to change if large changes has to be made.
   Consider a latch has to be changed from 16 to 32 bit's , that's a lot of wires to redraw.

2: This is where the HDL has it's advantages.
   But i will not go into a VHDL vs. Verilog war.
   Instictively i would go for Verilog because i have a C background.
   But i will continue to use VHDL , primarily because it forced me to drop the "C" (sequential) thinking.
   But also because VHDL seems to be the chosen language here in Europe.


HOMEWORK QUESTION 2
Use the schematic – block diagram design method to make a simple design of your choice.

Simple but time consuming


See attached zip

I have made a 1Hz blink led on my EPM240 board ,witch have a 50Mhz Clock
So i'll use 4 x HC390 dividers in a divide : 100 / 100 / 100 / 50 configuration.

It took a very long time compared with what i would have used in VHDL

It won't fit in the EPM3032 as it uses 39 Cells , but that's not a problem with my EPM240

Code: Select all

Flow Status   Successful - Thu Sep  4 19:54:19 2014
Quartus II 64-Bit Version   13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name   lesson10d
Top-level Entity Name   lesson10d
Family   MAX II
Device   EPM240T100C5
Timing Models   Final
Total logic elements   39 / 240 ( 16 % )
Total pins   3 / 80 ( 4 % )
Total virtual pins   0
UFM blocks   0 / 1 ( 0 % )


To small to really see , and the PDF is larger than 256k , so i can't upload a decent print of the schematic

lesson10d.png

HOMEWORK QUESTION 3
After getting a sneak peak at Verilog, VHDL and Schematic. Which method of building a
CPLD/FPGA image do you like the most? Why?

I like Verilog the most , but will use VHDL.
I will try not to use Schematic , as i need the VHDL training .....


Afterthought:

Well after havng tried the schematic for the 50.000.000 divider ,
i'm positive that i won't use the schematic for anything but
simple combinatoric logic. If i'll ever use it again.


Edit:
Btw. Why don't CPLD's have pullup/pulldown's like the FPGA's
I actually had to connect RESET to GND before my EPM240 would blink at 1Hz



/Bingo

I apologize for my delay as well in responding!

Thanks for attaching your design again. Your homework answers are all correct!

It was a pleasure to help you out throughout this course. Don't let the VHDL vs. Verilog debate steer you 100% in either direction. Xilinx and Altera are actually moving into a direction where both VHDL and Verilog files are used inter-mixed in designs and actually their top level designs are becoming more and more auto-generated HDL and you just write C/C++ code for an embedded processor in the FPGA (either soft or hard). So knowing both has its advantages (at very least being able to read both).

[Bingo600]

Hi Chris

Thank you for teking the time to overlook my ansvers , once again.
The course have been "just what i neded" in order to get started with real VHDL on real hardware.

And i have gotten some hands on in both the Quartus and the ISE world.

If anyone else want to get their hands "dirty" , and don't need the 5v tolerance.
Have a look@ebay or AliExpress for some nice offers.

My "best value for the money" is still this : Mini System Development Board ALTERA FPGA CycloneII EP2C5T144 for $13
http://www.ebay.com/itm/111242540701

The Max240 was almost the same price, but this one have many more resources , pull-up/downs , 2 PLL's and lot's of other goodies.

The development is the same as with a CPLD , with one extra step ... At the end you have to write the bitfile to the config eeprom on the board , if you want the design to survive a poweroff.

Most FPGA's don't have any built in flash/eeprom. And need to either read the bitfile from an external eeprom to FPGA Ram (done automaticly at powerup) , or have the bitfile programmed to FPGA Ram via jtag.

You'd use jtag during development , and save the final design into the config eeprom when the design is done.

Another bobus is that you don't have any flash wear issues like on a CPLD.


All i can say is : Try to take this course, if you need to get some hands on.
It's rewarding to see your first "blinky".

But if you're comming from a C background like me , don't mistake & for "and" ... It's actually the "concatenator" function in VHDL. "Think strcat() for std_logic vectors".
And make sure you read up on "Statemachines", if you want to do anything complicated like write to a LCD.

If Chris ever do a Part II , or a section 11..15 i'd love to get some better understanding of :
Synchronizing (flags) between processes. , and Statemachines.


Thanx for your time Chris

/Bingo