#3 Input and Output [Post Homework Here]

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ThePyroElectro
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#3 Input and Output [Post Homework Here]

Postby ThePyroElectro » Thu Jul 10, 2014 7:04 pm

A new lesson was posted today:
http://www.pyroelectro.com/edu/fpga/input_output/

Post your homework answers here to compare with everyone else!

Bingo600
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Re: #3 Input and Output [Post Homework Here]

Postby Bingo600 » Sat Jul 12, 2014 9:10 am

Hi Chris

Here is my homework

Btw: Did you mean "top" level" below , and were bitten by a spell checkker ?
How do you define a 1 bit logic input in a topic level entity in VHDL? What about a 1 bit logic
output?


In the port section you define a 1 bit input as:
<NAME>: in std_logic; -- semicolon on all entrys but the last in section

In the port section you define a 1 bit output as:
<NAME>: out std_logic; -- semicolon on all entrys but the last in section


Which input/output CMOS logic levels is the EPM3032A CPLD compatible with?


The EPM3032A CPLD is compatible with :
All VCC(io) : Input is compatible with 2.5v , 3.3v and 5.0v logic
Outputs depends on VCC(io) as V(ih) has to be met on the "receiving device".
Vcc(io) 2.5v : Output is compatible with 2.5v devices.
Vcc(io) 3.3v : Output is compatible with 3.3v and 5.0v devices. (low margin on the 5v , as 0.6*VCC(5v) is 3.0v)

For outputs driving TTL ot HCT (did you mean that instead of CMOS) , both VCC(io) would satisfy the input requirements TLL-V(ih) of 2.0v


What is the purpose of the 10kΩ pull down resistor connected to the push-button? What do
you think would happen if it wasn’t there?


Without it the CPLD input would be floating/undefined when the switch is not closed.
And the led would probably oscillate due to the input port doing the same.
If a CPLD is like a CMOS chip , you might destroy the port due to oscillation or statics.

Nitpicking

On my S3 FPGA i can set internal PullUp/PullDown inside the IO-Block , and prob avoid the need for the external PullDown.
My EE friend did advice that the button circuit oucht to draw 1..2 ma when closed , then the current flow would "burn off" the oxidation , and make the contacts "self cleaning". This usually mean that you have to use an external Pull resistor , as the internals usually have to high a ohmic value to meet the 1..2 ma.



There are some errors in the code.pdf (i cheated & pasted , and learned about syntax checkking)

Code: Select all

library ieee;
use ieee.std_logic_1164.all;
entity lesson2 is                <-- lesson 3
   port(
   BUTTON_0: in std_logic -- Pin 23       <-- Semicolon missing
   LED_0: out std_logic -- Pin 22
   );
end lesson2;                 <-- lesson 3

architecture rtl of lesson3 is
begin
   LED_0 <= BUTTON_0;
end rtl;


Question


Based on your drawing/division in the video of LAB A/B

Can i assume that there is a set of VCC pins for each block ?

9 VCC(io) LAB A
41 VCC(int) LAB A

29 VCC(io) LAB B
17 VCC(int) LAB B

Where did you find that info (about witch VCC pins belongs to witch LAB ?) , and how to draw the division lines of LAB A/B ?
If i look in the pinout PDF , i can only see LAB A/B designations for the IO pins. The VCC pins have a - in the table.

And i can't seem to (easily) find this info in the MAX3000A DS.

Question


In my "Pedroni book" , he uses BIT instead of std_logic.

It compiles if i change BOTH port definitions to BIT.

Code: Select all

library ieee;
use ieee.std_logic_1164.all;

entity lesson3 is
   port(
   BUTTON_0: in BIT; -- Pin 23
   LED_0: out BIT      -- Pin 22
   );
end lesson3;

architecture rtl of lesson3 is
begin
   LED_0 <= BUTTON_0;
end rtl;


BIT and std_logic is not 100% the same , as i started out just changing the Button def. to BIT , and then i got an error :

Error (10476): VHDL error at lesson3.vhd(13): type of identifier "BUTTON_0" does not agree with its usage as "std_logic" type


It's pointing at the assignment line : LED_0 <= BUTTON_0;

So BIT is NOT the same type as std_logic , but i suppose it is a "synonym".

/Bingo

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Re: #3 Input and Output [Post Homework Here]

Postby ThePyroElectro » Sat Jul 12, 2014 3:47 pm

Bingo600 wrote:Hi Chris

Here is my homework

Btw: Did you mean "top" level" below , and were bitten by a spell checkker ?
How do you define a 1 bit logic input in a topic level entity in VHDL? What about a 1 bit logic
output?


In the port section you define a 1 bit input as:
<NAME>: in std_logic; -- semicolon on all entrys but the last in section

In the port section you define a 1 bit output as:
<NAME>: out std_logic; -- semicolon on all entrys but the last in section


Which input/output CMOS logic levels is the EPM3032A CPLD compatible with?


The EPM3032A CPLD is compatible with :
All VCC(io) : Input is compatible with 2.5v , 3.3v and 5.0v logic
Outputs depends on VCC(io) as V(ih) has to be met on the "receiving device".
Vcc(io) 2.5v : Output is compatible with 2.5v devices.
Vcc(io) 3.3v : Output is compatible with 3.3v and 5.0v devices. (low margin on the 5v , as 0.6*VCC(5v) is 3.0v)

For outputs driving TTL ot HCT (did you mean that instead of CMOS) , both VCC(io) would satisfy the input requirements TLL-V(ih) of 2.0v


What is the purpose of the 10kΩ pull down resistor connected to the push-button? What do
you think would happen if it wasn’t there?


Without it the CPLD input would be floating/undefined when the switch is not closed.
And the led would probably oscillate due to the input port doing the same.
If a CPLD is like a CMOS chip , you might destroy the port due to oscillation or statics.


Thanks I updated the homework pdf.

Correct answers!

Yea, TTL and LVTTL. I'll omit the 'CMOS' from it. That word is inappropriate there.

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Re: #3 Input and Output [Post Homework Here]

Postby ThePyroElectro » Sat Jul 12, 2014 4:00 pm

Bingo600 wrote:
Nitpicking

On my S3 FPGA i can set internal PullUp/PullDown inside the IO-Block , and prob avoid the need for the external PullDown.
My EE friend did advice that the button circuit oucht to draw 1..2 ma when closed , then the current flow would "burn off" the oxidation , and make the contacts "self cleaning". This usually mean that you have to use an external Pull resistor , as the internals usually have to high a ohmic value to meet the 1..2 ma.


Internal pull-ups are typically calibrated to 100kΩ +/- 10%. They're pretty weak but for many cases they do the job. As for burning off oxidation, that's very dependent upon the device/button. I've never heard that before...interesting.

Bingo600 wrote:
Question


Based on your drawing/division in the video of LAB A/B

Can i assume that there is a set of VCC pins for each block ?

9 VCC(io) LAB A
41 VCC(int) LAB A

29 VCC(io) LAB B
17 VCC(int) LAB B

Where did you find that info (about witch VCC pins belongs to witch LAB ?) , and how to draw the division lines of LAB A/B ?
If i look in the pinout PDF , i can only see LAB A/B designations for the IO pins. The VCC pins have a - in the table.

And i can't seem to (easily) find this info in the MAX3000A DS.


On the MAX3000A datasheet it refers you...."See the Altera web site ( http://www.altera.com ) or the Altera Digital Library for pin–out information."

Which is here: http://www.altera.com/literature/lit-dp.jsp

Then you choose your device and which model, for us EPM3032ATC44-10:
http://www.altera.com/literature/lit-dp.jsp?category=MAX%203000A

There they have two text files and the PDF that we saw in the video.

There is no place that explicitly says these VCCIO pins go to this lab. Intuition from all the other FPGAs and CPLDs I've used told me. Perhaps they should document it better?! :|

Bingo600 wrote:
Question


In my "Pedroni book" , he uses BIT instead of std_logic.

It compiles if i change BOTH port definitions to BIT.

Code: Select all

library ieee;
use ieee.std_logic_1164.all;

entity lesson3 is
   port(
   BUTTON_0: in BIT; -- Pin 23
   LED_0: out BIT      -- Pin 22
   );
end lesson3;

architecture rtl of lesson3 is
begin
   LED_0 <= BUTTON_0;
end rtl;


BIT and std_logic is not 100% the same , as i started out just changing the Button def. to BIT , and then i got an error :

Error (10476): VHDL error at lesson3.vhd(13): type of identifier "BUTTON_0" does not agree with its usage as "std_logic" type


It's pointing at the assignment line : LED_0 <= BUTTON_0;

So BIT is NOT the same type as std_logic , but i suppose it is a "synonym".

/Bingo


I'm not 100% sure what your question here is. Perhaps BIT vs. Standard logic?

To start, BIT has only 2 states '0' or '1'. STD_LOGIC has several states U, Z, 0, 1, X....etc and because it is a different VHDL type you can't use a BIT to drive a std_logic signal.

However, you can use a BIT to drive a BIT since they're the same type, like we used a std_logic to drive another std_logic.

In my experience BIT is not used as often as STD_LOGIC. STD_LOGIC simply offers you more functionality both at run-time (for example: you can set outputs to 'Z' high-impedance) and during test-bench simulation (you can see U - uninitialized signals or X - unknown sourced signals).

Bingo600
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Re: #3 Input and Output [Post Homework Here]

Postby Bingo600 » Sat Jul 12, 2014 6:26 pm

ThePyroElectro wrote:I'm not 100% sure what your question here is. Perhaps BIT vs. Standard logic?

To start, BIT has only 2 states '0' or '1'. STD_LOGIC has several states U, Z, 0, 1, X....etc and because it is a different VHDL type you can't use a BIT to drive a std_logic signal.

However, you can use a BIT to drive a BIT since they're the same type, like we used a std_logic to drive another std_logic.

In my experience BIT is not used as often as STD_LOGIC. STD_LOGIC simply offers you more functionality both at run-time (for example: you can set outputs to 'Z' high-impedance) and during test-bench simulation (you can see U - uninitialized signals or X - unknown sourced signals).


That was excactly my question :oops:

And a very good ansver , thanx.

/Bingo

Bingo600
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Posts: 75
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Re: #3 Input and Output [Post Homework Here]

Postby Bingo600 » Sat Jul 12, 2014 6:29 pm

There is no place that explicitly says these VCCIO pins go to this lab. Intuition from all the other FPGAs and CPLDs I've used told me. Perhaps they should document it better?! :|


I actually think they should.

Suppose i want to use the cpld as a levelconverter , and use LAB A for 3v3 , and LAB B for 2v5.
It would be rather important now to reverse the power-pins for the LAB's , as i would fry the 2v5 device.

/Bingo

Roamin
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Re: #3 Input and Output [Post Homework Here]

Postby Roamin » Sat Jul 12, 2014 6:44 pm

How do you define a 1 bit logic input in a top level entity in VHDL?
What about a 1 bit logic output?

Code: Select all

entity example is
port(
ENTITY_NAME: in std_logic;
ENTITY_NAME2: out std_logic
);
end example;


*** The only thing confusing since i'm not familiar with vhdl at all is why the second entity declaration doesn't end with a semi colon ; , i'm guessing because the block ends right after and is closed after the ); ?


Which input/output logic levels is the EPM3032A CPLD compatible with?
3.3v and 2.5v CMOS type

What is the purpose of the 10kΩ pull down resistor connected to the push - button?
What do you think would happen if it wasn’t there?

The 10k pulls down towards GND reference to make sure both states high and low will be valid signals and not left floating.
The LED would always be on if the circuitry inside the CPLD is pulled high


Edit : On a side note, I received the kit earlier this week , only the be hit with another 18$ customs, on top of the 18$ shipping I had already paid. And the kit was shipped with 10 x 100 ohm resistors instead of 470 ohm resistors...

Bingo600
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Posts: 75
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Re: #3 Input and Output [Post Homework Here]

Postby Bingo600 » Sat Jul 12, 2014 9:10 pm

Roamin wrote:Edit : On a side note, I received the kit earlier this week , only the be hit with another 18$ customs, on top of the 18$ shipping I had already paid. And the kit was shipped with 10 x 100 ohm resistors instead of 470 ohm resistors...


I'm using an EPM240 board
See here
viewtopic.php?f=26&t=819

/Bingo
Attachments
itead-epm240.zip
(116.72 KiB) Downloaded 419 times

ThePyroElectro
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Re: #3 Input and Output [Post Homework Here]

Postby ThePyroElectro » Sun Jul 13, 2014 6:02 pm

Roamin wrote:How do you define a 1 bit logic input in a top level entity in VHDL?
What about a 1 bit logic output?

Code: Select all

entity example is
port(
ENTITY_NAME: in std_logic;
ENTITY_NAME2: out std_logic
);
end example;


*** The only thing confusing since i'm not familiar with vhdl at all is why the second entity declaration doesn't end with a semi colon ; , i'm guessing because the block ends right after and is closed after the ); ?


Which input/output logic levels is the EPM3032A CPLD compatible with?
3.3v and 2.5v CMOS type

What is the purpose of the 10kΩ pull down resistor connected to the push - button?
What do you think would happen if it wasn’t there?

The 10k pulls down towards GND reference to make sure both states high and low will be valid signals and not left floating.
The LED would always be on if the circuitry inside the CPLD is pulled high


Edit : On a side note, I received the kit earlier this week , only the be hit with another 18$ customs, on top of the 18$ shipping I had already paid. And the kit was shipped with 10 x 100 ohm resistors instead of 470 ohm resistors...


Hi Roamin,

Correct Answers!

That's just the structure of VHDL. No semicolon on the last definition of the port. Don't ask me why, it's just the language!

Damn, customs fees are lame :-(. 100Ω ohm resistors would still work, your LEDs will just be brighter! Hehe :P .
Either way, go tell those guys at Gadgetory to get you the right parts -> http://gadgetory.com/index.php?route=information/contact.

Roamin
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Posts: 6
Joined: Mon Jun 30, 2014 11:02 pm

Re: #3 Input and Output [Post Homework Here]

Postby Roamin » Mon Jul 14, 2014 12:06 pm

I understand that the LEDs will be brighter, I just didn't take time looking at the max 3000a datasheet to see what is the maximum current that can be sourced out of the CPLD. At 470, the LED would light with 3mA , but with 100 ohm the current would be 16mA .. a big difference , although I doubt that the max source current is less than at least 20ma.

Just a quick note on my background, I am and electronics technician since 2001 , I can program in C , and used to program PICs in ASM, but I haven't touched it in a long long time, although I still understand how it works and all. I've been mainly programming atmega32u2 for the past few years. My next step is to learn VHDL, I'm curious to learn more about CPLDs and FPGAs and see if I would actually use those more often than MCUs.

The first tutorials are too short :( I want to do more than just toggle LEDs for a week ;) I am patiently awaiting the next ones.

And , Thanks Pyro for doing the tutorials, it's very appreciated.

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Re: #3 Input and Output [Post Homework Here]

Postby ThePyroElectro » Mon Jul 14, 2014 2:53 pm

Roamin wrote:I understand that the LEDs will be brighter, I just didn't take time looking at the max 3000a datasheet to see what is the maximum current that can be sourced out of the CPLD. At 470, the LED would light with 3mA , but with 100 ohm the current would be 16mA .. a big difference , although I doubt that the max source current is less than at least 20ma.

Just a quick note on my background, I am and electronics technician since 2001 , I can program in C , and used to program PICs in ASM, but I haven't touched it in a long long time, although I still understand how it works and all. I've been mainly programming atmega32u2 for the past few years. My next step is to learn VHDL, I'm curious to learn more about CPLDs and FPGAs and see if I would actually use those more often than MCUs.

The first tutorials are too short :( I want to do more than just toggle LEDs for a week ;) I am patiently awaiting the next ones.

And , Thanks Pyro for doing the tutorials, it's very appreciated.


Hi Roamin,

On FPGAs its typical to have 8mA and 16mA outputs that you can actually set within the tool!

For the CPLD we're using though, page 22 of the datasheet:

Iout DC output current, per pin Min: –25mA Max: 25mA


Your background is a lot stronger than the typical student, so the first 3-4 lessons will probably seem a little slow. Lesson8 and Lesson9 will probably be the most interesting to you, since they are applications of VHDL.

Typically CPLDs are used in conjunction with a microcontroller. In some cases you can get a microcontroller+cpld in one IC like a PSOC from cypress semiconductor.

FPGAs on the other hand are so large that you can build soft-microcontroller processors inside of them through either the altera NIOS II tools or the Xilinx EDK tool suite. Something to consider after you've finished this course and are ready for more ;-)


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