4-bit Shift Register in VHDL

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menix
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4-bit Shift Register in VHDL

Postby menix » Mon Apr 13, 2015 12:37 pm

Hi,

Is there a way to code and simulate a 4-bit shift register with components from this Course?

Thanks,
Milos

ThePyroElectro
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Re: 4-bit Shift Register in VHDL

Postby ThePyroElectro » Mon Apr 13, 2015 4:41 pm

menix wrote:Hi,

Is there a way to code and simulate a 4-bit shift register with components from this Course?

Thanks,
Milos


Hi Milos,

I don't believe we have a shift register example in this course and we didn't cover test benches for simulation either.

However, there's a lot of good resources out on the web. Here's one that you might find useful as it relates to your request:

3-Bit Shift Register VHDL Code
http://esd.cs.ucr.edu/labs/tutorial/shifter.vhd

3-Bit Shift Register VHDL Test Bench Simulation
http://esd.cs.ucr.edu/labs/tutorial/tb_shifter.vhd

menix
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Posts: 4
Joined: Sat Apr 11, 2015 11:46 pm

Re: 4-bit Shift Register in VHDL

Postby menix » Mon Apr 13, 2015 8:41 pm

ThePyroElectro wrote:
menix wrote:Hi,

Is there a way to code and simulate a 4-bit shift register with components from this Course?

Thanks,
Milos


Hi Milos,

I don't believe we have a shift register example in this course and we didn't cover test benches for simulation either.

However, there's a lot of good resources out on the web. Here's one that you might find useful as it relates to your request:

3-Bit Shift Register VHDL Code
http://esd.cs.ucr.edu/labs/tutorial/shifter.vhd

H

3-Bit Shift Register VHDL Test Bench Simulation
http://esd.cs.ucr.edu/labs/tutorial/tb_shifter.vhd



Hi Pyro,

Thank you for your quick response.
I took a look at those link but i'm not familiar with test bench simulation. I'll dive into that these days.
On the other hand, what i've found, was an interesting code that i could understand in some book about digital electronics.
This is the code:

Code: Select all

library ieee;
use ieee.std_logic_1164.all;

entity dflipflop is
   port(d,clk   : in std_logic;
        q      : out std_logic);
end dflipflop;

architecture arc of dflipflop is
begin
   process (clk)
   begin
      if (clk'event and clk='1') then q <= d;
      end if;
   end process;
end arc;

library ieee;
use ieee.std_logic_1164.all;

entity shiftreg is
      port(serial_in,cp   : in std_logic;
           q3,q2,q1,q0      : buffer std_logic);
end shiftreg;

architecture arc of shiftreg is
   component dflipflop
   port(d,clk   : in std_logic;
        q      : out std_logic);
   end component;
begin
   ff3: dflipflop PORT MAP (d=> serial_in, clk=>cp,q=>q3);
   ff2: dflipflop PORT MAP (d=> q3, clk=>cp,q=>q2);
   ff1: dflipflop PORT MAP (d=> q2, clk=>cp,q=>q1);
   ff0: dflipflop PORT MAP (d=> q1, clk=>cp,q=>q0);
end arc;


I compiled and programmed the cpld with that code and everything worked just fine. The only problem is that clock signal. Whenever i push the button that represents the data (d) it lights up the first LED, even though the the button that represents the clock (cp) is not pushed. On the other hand if only clock is ON, the first LED goes off which is proper behavior. I wonder how come when i push the clock and the data button nothing happens. This line:

Code: Select all

if (clk'event and clk='1') then q <= d;
seems to fail when data button and clock button are pushed together.
When i tried another design with single D flip flip, the only time LED would turn ON/OFF is when the clock button was pressed which is as i expected.
My breadboard:
Image

ThePyroElectro
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Re: 4-bit Shift Register in VHDL

Postby ThePyroElectro » Tue Apr 14, 2015 12:49 am

menix wrote:Hi Pyro,

Thank you for your quick response.
I took a look at those link but i'm not familiar with test bench simulation. I'll dive into that these days.
On the other hand, what i've found, was an interesting code that i could understand in some book about digital electronics.
This is the code:

Code: Select all

...
....
...
...


I compiled and programmed the cpld with that code and everything worked just fine. The only problem is that clock signal. Whenever i push the button that represents the data (d) it lights up the first LED, even though the the button that represents the clock (cp) is not pushed. On the other hand if only clock is ON, the first LED goes off which is proper behavior. I wonder how come when i push the clock and the data button nothing happens. This line:

Code: Select all

if (clk'event and clk='1') then q <= d;
seems to fail when data button and clock button are pushed together.
When i tried another design with single D flip flip, the only time LED would turn ON/OFF is when the clock button was pressed which is as i expected.
My breadboard:


Hi Milos,

Which pins are connected to clock and data?

If pin 27 is part of the design that might explain your problem as the wires don't connect to the button. Furthermore the blue wire doesn't connect to the power bus, which would be necessary to send a +0v or +5v to pin27 by pressing the button. Currently the button's output would always be gnd +0v.

Image

If you're using pin23 and pin25 for your clk & serial_in inputs I'll have to scratch my head and think a little harder about the problem.

wingsio
Newbie Pyro
Posts: 4
Joined: Wed Jul 19, 2017 8:51 am

Re: 4-bit Shift Register in VHDL

Postby wingsio » Mon Jul 24, 2017 9:56 am

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wingsio


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