S3E Lesson7
Posted: Sat Aug 09, 2014 2:46 pm
Chris here is my implementation on the S3E Starterboard.
ISE wasn't really happy , i got two warnings
File : lesson7-bad.vhd
/Bingo
ISE wasn't really happy , i got two warnings
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
slice components. The resulting carry chain will have suboptimal timing.
Mcompar_ticks_cmp_ge0000_cy<12>
Mcount_ticks_cy<0>
WARNING:Route:455 - CLK Net:hz_10 may have excessive skew because
File : lesson7-bad.vhd
Code: Select all
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lesson7 is
Generic ( osc_freq: natural := 50000000);
port(
RESET: in std_logic; --"btn_south" LOC = "K17"
clk: in std_logic; --50Mhz Clock
BUTTON: in std_logic; --"btn_west" LOC = "D18"
LED_BTN: out std_logic; --LED7
SEG7: out std_logic_vector(6 downto 0) --LED 6..0
);
end lesson7;
architecture rtl of lesson7 is
signal data: std_logic;
signal bcd_value: std_logic_vector(3 downto 0);
signal hz_25m: std_logic :='0';
signal hz_10: std_logic :='0';
begin
--First Process
DATA_REGISTER_0: process(RESET,hz_10,BUTTON)
begin
if RESET = '1' then
data <= '0';
elsif rising_edge(hz_10) then
data <= BUTTON;
end if;
end process DATA_REGISTER_0;
LED_BTN <= data;
--Second Process
TIMER_0: process(RESET,hz_10)
begin
if RESET = '1' then
bcd_value <= "0000";
elsif rising_edge(hz_10) then
bcd_value <= bcd_value + 1;
end if;
end process TIMER_0;
-- 50Mhz to 25Mhz predivide
CLOCK_DIV2: process(clk,RESET)
begin
if RESET = '1' then
hz_25m <= '0';
elsif rising_edge(clk) then
hz_25m = not hz_25m;
end if;
end if;
end process CLOCK_DIV2;
-- 10HZ Clock Process
CLOCK_10HZ: process(hz_25m,RESET)
VARIABLE ticks:integer range 0 to ((osc_freq/10)/2)-1;
begin
if RESET = '1' then
ticks:=0;
elsif rising_edge(clk) then
ticks:=ticks+1;
if ticks >=(((osc_freq/10)/2)/2)-1 then
hz_10 <= not hz_10;
ticks:=0;
end if;
end if;
end process CLOCK_10HZ;
-- HC4511 Process (bcd to 7seg driver)
-- http://www.ti.com/lit/ds/symlink/cd74hc4511.pdf
-- Inspired by http://vhdlguru.blogspot.se/2010/03/vhdl-code-for-bcd-to-7-segment-display.html
-- But changed to "active high" led segments.
--
HC4511: process(hz_10,bcd_value,RESET)
begin
if RESET = '1' then
SEG7 <= "1111110"; -- '0'
elsif rising_edge(hz_10) then
case bcd_value is
when "0000"=> SEG7 <="1111110"; -- '0'
when "0001"=> SEG7 <="0110000"; -- '1'
when "0010"=> SEG7 <="1101101"; -- '2'
when "0011"=> SEG7 <="1111001"; -- '3'
when "0100"=> SEG7 <="0110011"; -- '4'
when "0101"=> SEG7 <="1011011"; -- '5'
when "0110"=> SEG7 <="1011111"; -- '6'
when "0111"=> SEG7 <="1110000"; -- '7'
when "1000"=> SEG7 <="1111111"; -- '8'
when "1001"=> SEG7 <="1111011"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> SEG7 <="0000000";
end case;
end if;
end process HC4511;
end rtl;
/Bingo