Here is my homework
What are some advantages of building CPLD hardware modules that operate in parallel?
The logic flows are independant (as in per process), that makes all processes flow execute simoultainously (parallel)
This capability enables us to get a FPGA/CPLD to act as if it were many individual external "logic chips".
One process per "chip".
HOMEWORK QUESTION 2
Create a new CPLD project and build two combinatorial logic statements that operate in
parallel: Y = (A + BC) , Z = (D + E + F). Show the RTL viewer output to prove they will be
I had to be sure about the boolean expressions , and had to look up the operators + = "or" and * (or "Nothing") = "and"http://www.doc.ic.ac.uk/~dfg/hardware/H ... ture01.pdf
I translate the requirements to be: A process where Y = (A or (B and C)) , and one where Z = (D or E or F)
This is my VHDL code.
Code: Select all
entity lesson7a is
A,B,C: in std_logic;
Y: out std_logic;
D,E,F: in std_logic;
Z: out std_logic
architecture rtl of lesson7a is
BLK_0 : process(A,B,C)
Y <= (A or (B and C));
end process BLK_0;
BLK_1 : process(D,E,F)
Z <= (D or E or F);
end process BLK_1;
And the RTL Viever
HOMEWORK QUESTION 3
In lesson 7 we gave an example of bit-coin mining, where a CPLD/FPGA would out-perform a
processor. Can you think of another example?
Crypto key breaking
Polygon drawing/shading (Graphics)
HighSpeed Communication / Interfacing (PCI Bus etc).
LED Controlling (Flatpanels etc.)