#6 Binary Timer [Post Homework Here]

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ThePyroElectro
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#6 Binary Timer [Post Homework Here]

Postby ThePyroElectro » Thu Jul 31, 2014 10:51 pm

A new lesson was posted today:
http://www.pyroelectro.com/edu/fpga/binary_counter/

Post your homework answers here to compare with everyone else!

Bingo600
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Posts: 75
Joined: Sat Jun 28, 2014 7:22 am

Re: #6 Binary Timer [Post Homework Here]

Postby Bingo600 » Fri Aug 01, 2014 6:06 pm

Hi Chris

Here is my homework "made in Sweden" :-)


HOMEWORK QUESTION 1
What is the difference between the 74HC193 timer/counter module and the one we designed
for a CPLD?

1: The 74HC193 has a /LOAD (Parallel load enable) , ours does not.
2: The 74HC193 has a CK_UP and a CK_DWN pin, ours only have the CK_UP (Clock).

HOMEWORK QUESTION 2
Using what you learned in this lesson to build an 8-bit binary counter using VHDL.


Code: Select all

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lesson6 is
   port(
         RESET: in std_logic; --PIN_44
         CLOCK: in std_logic; --PIN_37
         LED:     out std_logic_vector(7 downto 0) --PIN_19 to PIN_22
   );
end lesson6;

architecture rtl of lesson6 is
   signal count : std_logic_vector(7 downto 0);
begin
   TIMER_0 : process(RESET,CLOCK)
   begin
      if RESET = '1' then
         count <= "00000000";
      elsif rising_edge(CLOCK) then
         count <= count + 1;
      end if;
   end process TIMER_0;
   LED <= count;
end rtl;   


Screenshot-RTL Viewer - -home-cfo-x-altera-pyro-course-Lesson6-lesson6 - lesson6-1.png
Screenshot-RTL Viewer - -home-cfo-x-altera-pyro-course-Lesson6-lesson6 - lesson6-1.png (54.31 KiB) Viewed 7114 times


Ohh ... And i was bitten by the newbie : expression ""0000"" has 4 elements ; expected 8 elements.
I just changed the 3 downto , to 7 downto , and did the "classic" goof' i guess :-)


HOMEWORK QUESTION 3
Search online to find more information about the library: ieee.std_logic_unsigned.all
Other than using the ‘+’ operator for addition of standard logic, name 2 other functions this
library offers us to use.


From here
http://www.csee.umbc.edu/portal/help/VHDL/stdpkg.html

On the std_logic_unsigned page
http://www.csee.umbc.edu/portal/help/VH ... signed.vhd

One can see that this library offers :

+ , - , *

< , > , <= , >= , = and /= -- (strange they use /= instead if !=) , does that come from the way you usually write an "Active-Low Chip Enable" = /CE ??

SHL , SHR -- I suppose shift L & R

This pdf explains a bit more about usage
www-micro.deis.unibo.it/~drossi/Dida02/lezioni/IEEE_Standard_Packages.pdf


/Bingo

Bingo600
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Posts: 75
Joined: Sat Jun 28, 2014 7:22 am

Re: #6 Binary Timer [Post Homework Here]

Postby Bingo600 » Fri Aug 01, 2014 6:16 pm

It was easier to bring my Xilins S3E EDU board to Sweden.

So i haven't done the real hardware on my EPM240 , just did the VHDL in Quartus.

I did the real hardware on the S3E board in ISE , and quiclky discovered that 50Mhz into a 4-bit led counter ==> To fast to see blinking.
So i dug out the 10Hz ticker i used in lesson 5 , and then i could follow the binary counting.

Code: Select all

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lesson6 is
   Generic ( osc_freq: natural := 50000000);
   port(
         RESET: in std_logic; --PIN_44
         clk: in std_logic; --PIN_37
         LED:     out std_logic_vector(7 downto 0) --PIN_19 to PIN_22
   );
end lesson6;

architecture rtl of lesson6 is
   signal count : std_logic_vector(7 downto 0);
   signal hz_10: std_logic :='0';
begin

   CLOCK_10HZ: process(clk)
   VARIABLE ticks:integer range 0 to (osc_freq/10)-1;
   begin
   if rising_edge(clk) then
      ticks:=ticks+1;
      if ticks >=((osc_freq/10)/2)-1 then
         hz_10 <= not hz_10;
         ticks:=0;
      end if;
   end if;
   end process CLOCK_10HZ;
   
   TIMER_0 : process(RESET,hz_10)
   begin
      if RESET = '1' then
         count <= "00000000";
      elsif rising_edge(hz_10) then
         count <= count + 1;
      end if;
   end process TIMER_0;
   LED <= count;
end rtl;   


/Bingo


Ps: The RTL viwer in ISE sucks

Bingo600
Newbie Pyro
Posts: 75
Joined: Sat Jun 28, 2014 7:22 am

Re: #6 Binary Timer [Post Homework Here]

Postby Bingo600 » Fri Aug 01, 2014 6:32 pm

Ohh :oops: :oops:

Once again i left RESET unassigned in the ucf file , and forgot to reset the "ticks counter" when RESET was pressed.

New implementation here:

Code: Select all

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lesson6 is
   Generic ( osc_freq: natural := 50000000);
   port(
         RESET: in std_logic; --PIN_44
         clk: in std_logic; --PIN_37
         LED:     out std_logic_vector(7 downto 0) --PIN_19 to PIN_22
   );
end lesson6;

architecture rtl of lesson6 is
   signal count : std_logic_vector(7 downto 0);
   signal hz_10: std_logic :='0';
begin

   CLOCK_10HZ: process(clk,RESET)
   VARIABLE ticks:integer range 0 to (osc_freq/10)-1;
   begin
   if RESET = '1' then
      ticks:=0;
   elsif rising_edge(clk) then
      ticks:=ticks+1;
      if ticks >=((osc_freq/10)/2)-1 then
         hz_10 <= not hz_10;
         ticks:=0;
      end if;
   end if;
   end process CLOCK_10HZ;
   
   TIMER_0 : process(RESET,hz_10)
   begin
      if RESET = '1' then
         count <= "00000000";
      elsif rising_edge(hz_10) then
         count <= count + 1;
      end if;
   end process TIMER_0;
   LED <= count;
end rtl;   


/Bingo

Is this really the best ISE RTL viewer can do ?
RTL-print.pdf.zip
(10.14 KiB) Downloaded 405 times



Btw: I briefly looked at DCM (as you mentioned it) , but it doesn't seem to be able to divide 50Mhz down to 10Hz
As per here : http://forums.xilinx.com/t5/Design-Entr ... td-p/28556

I might be able to cascade two , but there are just 4 in the S3E - 500

ThePyroElectro
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Posts: 1181
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Contact:

Re: #6 Binary Timer [Post Homework Here]

Postby ThePyroElectro » Mon Aug 04, 2014 6:46 pm

Bingo600 wrote:Hi Chris

Here is my homework "made in Sweden" :-)


HOMEWORK QUESTION 1
What is the difference between the 74HC193 timer/counter module and the one we designed
for a CPLD?

1: The 74HC193 has a /LOAD (Parallel load enable) , ours does not.
2: The 74HC193 has a CK_UP and a CK_DWN pin, ours only have the CK_UP (Clock).
...
...
...
One can see that this library offers :

+ , - , *

< , > , <= , >= , = and /= -- (strange they use /= instead if !=) , does that come from the way you usually write an "Active-Low Chip Enable" = /CE ??

SHL , SHR -- I suppose shift L & R

This pdf explains a bit more about usage
www-micro.deis.unibo.it/~drossi/Dida02/lezioni/IEEE_Standard_Packages.pdf


/Bingo


Very good answers. Yes, I agree...I'm very used to != so it took some getting used to /= when I first started with VHDL. As a side note, the Verilog HDL language has != and !==.

Bingo600 wrote:Ps: The RTL viwer in ISE sucks
...
...
...
Is this really the best ISE RTL viewer can do ?


Speaking in terms of digital logic: TRUE. But it also depends on how you write your code. If you write unfriendly VHDL/Verilog code the synthesis tool can do weird things. Typically the RTL viewer or Xilinx's 'Technology Viewer' are just used to double check that the synthesizer is indeed building things up the way you intended, so I treat it as a visual alternative to looking through all the log files.

I would agree that Quartus' RTL Viewer is fairly better, but I'm bias to say that the Quartus tools are also 'funner' to use.

Other (potentially) better RTL viewers would be a 3rd party application like this: http://www.concept.de/StarVision.html

Bingo600 wrote:Btw: I briefly looked at DCM (as you mentioned it) , but it doesn't seem to be able to divide 50Mhz down to 10Hz
As per here : http://forums.xilinx.com/t5/Design-Entr ... td-p/28556

I might be able to cascade two , but there are just 4 in the S3E - 500


That doesn't entirely surprise me. But it would sure seems to be a waste to use two DCMs to generate a lowly and super slow 10 Hz signal.

Either way, in reality you probably will never need to generate such slow signals for an input clock. That's what the DCMs are primarly there for. Taking a faster 50-300 MHz clock signal and bringing it down to a stable 10-50 MHz for your FPGA logic.

We do everything super slow in the FPGA/CPLD course because then we can watch the logic as it happens, instead of it going insanely fast. We did the same thing in the introduction to digital electronics course, used a 555 timer with 10 Hz first, then tested the logic with a 20 MHz oscillator. 20 MHz is too damn fast to watch the logic :lol: .


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