S3E lesson5

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Bingo600
Newbie Pyro
Posts: 75
Joined: Sat Jun 28, 2014 7:22 am

S3E lesson5

Postby Bingo600 » Sun Jul 27, 2014 2:39 pm

Chris i have done lesson5 on my S3E starterboard , and was bitten a few times :shock:

First i got bitten by the "reset" that i did not connect in the ucf file , and apparently 2 times the design worked (pure luck i guess , the fitter must have chosen a pin that was low) , then i corrected a small detail , and now nothing worked.
I scratched my head quite a bit until it suddently hit me that it could be eset being held high.

I did connect reset to "button_south" that has ab active pulldown , and connects to vcc. Now the design began to work again. :oops:


As i only have a 50MHz osc on the S3E board , i had to divide that down to the desired 10Hz on an other procedure , in order to be able to simulate the "lesson5".

I have made 2 versions , where one is heavily inspired by a demo that came wit my EPM240 cpld board , and the other 2'nd one is my own.

But the first one is strange in the "clock" , it has a duration of 340 ms , where i would have expected 200ms as im my 2'nd design.

/Bingo

Bingo600
Newbie Pyro
Posts: 75
Joined: Sat Jun 28, 2014 7:22 am

Re: S3E lesson5

Postby Bingo600 » Sun Jul 27, 2014 2:42 pm

Lesson5-1

The thought here in CLOCK_10HZ , was to make 0 .. (50Mhz/10)/2 a low , and (50Mhz/10)/2 to (50Mhz/10) a high
But it blinks slower than the 5hz , my scope says approx 334 ms.

less-5-1.png
less-5-1.png (3.37 KiB) Viewed 5924 times


Code: Select all

library ieee;
use ieee.std_logic_1164.all;

entity lesson5 is
Generic ( osc_freq: natural := 50000000);
port(
   btn_west:      in   std_logic; --
   clk:         in   std_logic; --
   btn_south:   in   std_logic; --
   led_0:      out std_logic; --
   led_1:      out std_logic --
   );
end lesson5;

architecture rtl of lesson5 is
signal blink: std_logic;
signal data: std_logic;
signal hz_10: std_logic;

begin
   DATA_REGISTER_0: process(hz_10,btn_west,btn_south)
   begin
   if btn_west = '1' then
      data <= '0';
      blink <= '0';
   elsif rising_edge(hz_10) then
      data <= btn_south;
      blink <= not blink;
   end if;
   end process DATA_REGISTER_0;
   
   CLOCK_10HZ: process(clk)
   VARIABLE ticks:integer range 0 to (osc_freq/10)-1;
   begin
   if rising_edge(clk) then
      if ticks<=((osc_freq/10)/2)-1 then
         hz_10 <= '0';
         ticks:=ticks+1;
      elsif
         ticks >= ((osc_freq/10)/2)-1 and ticks <= (osc_freq/10)-1 then
         hz_10 <= '1';
         ticks:=ticks+1;
      else
         ticks:=0;
      end if;
   end if;
   end process;
   
   led_0 <= blink;
   led_1 <= data;
end rtl;   
   




Another thing here is that i think i have an "overlap" in the elseif

Code: Select all

ticks >= ((osc_freq/10)/2)-1 and ticks <= (osc_freq/10)-1 then


Should prob be

Code: Select all

ticks >= ((osc_freq/10)/2) and ticks <= (osc_freq/10)-1 then


As the line above would also match "2500000-1" due to the equal

Code: Select all

if ticks<=((osc_freq/10)/2)-1 then



Is that correct ?
Could that screv up my timing so much ?
What about the hz_10 assignment , as i have understand it would prob be '1' , as signals uses the last assignment or ?

/Bingo
Attachments
5-1-print.pdf.zip
(29 KiB) Downloaded 309 times

Bingo600
Newbie Pyro
Posts: 75
Joined: Sat Jun 28, 2014 7:22 am

Re: S3E lesson5

Postby Bingo600 » Sun Jul 27, 2014 3:06 pm

Lesson5-3 (5-2 was a working revision and omitted)

The thought here in CLOCK_10HZ , was to count from 0 .. ((50Mhz/10)/2)-1. And then "Flip" hz_10.
This one has the timing correct 200ms.
less-5-3.png
less-5-3.png (3.32 KiB) Viewed 5923 times


But gives a warning ... why ??
WARNING:Route:455 - CLK Net:hz_10 may have excessive skew because


To my surprise it also used more logic than the "complicated 5-1" ( Why can't i add pdf files :-( )
5-3-print.pdf.zip
(28.99 KiB) Downloaded 325 times



Code: Select all

library ieee;
use ieee.std_logic_1164.all;

entity lesson5 is
Generic ( osc_freq: natural := 50000000);
port(
   btn_west:      in   std_logic; --
   clk:         in   std_logic; --
   btn_south:   in   std_logic; --
   led_0:      out std_logic; --
   led_1:      out std_logic --
   );
end lesson5;

architecture rtl of lesson5 is
signal blink: std_logic;
signal data: std_logic;
signal hz_10: std_logic :='0';

begin
   DATA_REGISTER_0: process(hz_10,btn_west,btn_south)
   begin
   if btn_west = '1' then
      data <= '0';
      blink <= '0';
   elsif rising_edge(hz_10) then
      data <= btn_south;
      blink <= not blink;
   end if;
   end process DATA_REGISTER_0;
   
   CLOCK_10HZ: process(clk)
   VARIABLE ticks:integer range 0 to (osc_freq/10)-1;
   begin
   if rising_edge(clk) then
      ticks:=ticks+1;
      if ticks >=((osc_freq/10)/2)-1 then
         hz_10 <= not hz_10;
         ticks:=0;
      end if;
   end if;
   end process;
   
   led_0 <= blink;
   led_1 <= data;
end rtl;   

-- WARNING:Route:455 - CLK Net:hz_10 may have excessive skew because    



/Bingo

ThePyroElectro
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Re: S3E lesson5

Postby ThePyroElectro » Mon Jul 28, 2014 2:14 am

Bingo600 wrote:Lesson5-1

The thought here in CLOCK_10HZ , was to make 0 .. (50Mhz/10)/2 a low , and (50Mhz/10)/2 to (50Mhz/10) a high
But it blinks slower than the 5hz , my scope says approx 334 ms.

Code: Select all

if rising_edge(clk) then
      if ticks<=((osc_freq/10)/2)-1 then
         hz_10 <= '0';
         ticks:=ticks+1;
      elsif
         ticks >= ((osc_freq/10)/2)-1 and ticks <= (osc_freq/10)-1 then
         hz_10 <= '1';
         ticks:=ticks+1;
      else
         ticks:=0;
      end if;
   end if;
   end process;
   
   led_0 <= blink;
   led_1 <= data;
end rtl;


Is that correct ?
Could that screv up my timing so much ?
What about the hz_10 assignment , as i have understand it would prob be '1' , as signals uses the last assignment or ?

/Bingo


I'm not sure exactly why it is putting out a 333mS signal. Something in the If/Else if statements isn't happy. But just while looking at it, that code is more complex than it really needs to be.

I would simplify it down to something like

Code: Select all

 --Sudo Code
if ticks = 25,000,000 then
      hz_10 <= not hz_10;
      ticks := 0;
end if;

ticks = ticks + 1;


The key is to remember that you're putting together hardware blocks to create specific output signals.

For a divider we just need a counter to count up to half the value of our desired output frequency signal, which then triggers a simple flip-flop back and forth between a 0 and 1 each time the timer 'overflows' or reaches our specified value.

....which apparently is exactly what you already did in your 3rd iteration for lesson5....

Bingo600 wrote:Lesson5-3 (5-2 was a working revision and omitted)

But gives a warning ... why ??
WARNING:Route:455 - CLK Net:hz_10 may have excessive skew because


/Bingo


This warning is possibly due to the fact that you're using a signal as a clock and therefore it doesn't have access to the global clock routing grid, combined with the fact that we haven't been constraining the timing of our inputs/outputs/clock signals. So the synthesis/place & route tools are just warning us that at higher clock speeds, you'll likely experience signal skew. At 5-10 Hz, no way will there be any skew :P .

These are more advanced ideas that I don't intend to teach in this course. They are best studied after you have a solid foundation in using the tool and writing VHDL. (Another advanced note: In modern FPGAs we typically never use dividers like this to get frequencies we need, instead we use modules, like DCMs (Digital Clock Managers) which will control things like frequency and skew very carefully).


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