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### #4 Combinatorial Logic [Post Homework Here]

Posted: Thu Jul 17, 2014 8:14 pm
A new lesson was posted today:
http://www.pyroelectro.com/edu/fpga/combinatorial_logic/

### Re: #4 Combinatorial Logic [Post Homework Here]

Posted: Sat Jul 19, 2014 12:35 pm
Chris i'm in Sweden this weekend.
Will do the homework when i get home

/BIngo

### Re: #4 Combinatorial Logic [Post Homework Here]

Posted: Sun Jul 20, 2014 2:37 am
Bingo600 wrote:Chris i'm in Sweden this weekend.
Will do the homework when i get home

/BIngo

No rush. Don't get stockholm syndrome .

### Re: #4 Combinatorial Logic [Post Homework Here]

Posted: Mon Jul 21, 2014 4:58 pm
Hi Chris here is my homework for lesson4

HOMEWORK QUESTION 1
Name 5 combinatorial logic operators that you can use in VHDL.

AND,OR,XOR,NOT,NAND,NOR

HOMEWORK QUESTION 2
Is it possible to implement all of the logic in a 74_08 (Quad 2-input AND Gate) logic IC inside
of our EPM3032A CPLD? (please explain why yes/no).

Yes it is

Code: Select all

`library ieee;use ieee.std_logic_1164.all;entity lesson4_7408 isport(   --    -- Modelled after NXP 74F08    -- http://www.nxp.com/documents/data_sheet/74F08.pdf   --   D0a:    in std_logic;    D0b:    in std_logic;    Q0:      out std_logic;   --   D1a:    in std_logic;    D1b:    in std_logic;    Q1:      out std_logic;   --   D2a:    in std_logic;    D2b:    in std_logic;    Q2:      out std_logic;   --   D3a:    in std_logic;    D3b:    in std_logic;    Q3:      out std_logic);end lesson4_7408;architecture rtl of lesson4_7408 isbegin--Logic to implement a 74F08   Q0 <= D0a AND D0b;   Q1 <= D1a AND D1b;   Q2 <= D2a AND D2b;   Q3 <= D3a AND D3b;   end rtl;`

RTL Viewer
Screenshot-RTL Viewer - -home-cfo-x-altera-pyro-course-lesson4-7408-lesson4-7408 - lesson4-7408.png (52.51 KiB) Viewed 19559 times

HOMEWORK QUESTION 3
Pretend A,B,C,D and Y are std_logic signals. Translate
This logic diagram to VHDL combinatorial logic.

Code: Select all

`library ieee;use ieee.std_logic_1164.all;entity lesson4_q3 isport(   a:    in std_logic;    b:    in std_logic;    c:    in std_logic;    d:    in std_logic;    y:      out std_logic);end lesson4_q3;architecture rtl of lesson4_q3 isbegin--Logic to implement a lesson4 question 3   y <=  d NAND ((NOT c) or (a AND b));   end rtl;`

RTL Viewer
Screenshot-RTL Viewer - -home-cfo-x-altera-pyro-course-lesson4_q3-lesson4_q3 - lesson4_q3.png (44.71 KiB) Viewed 19559 times

### Re: #4 Combinatorial Logic [Post Homework Here]

Posted: Mon Jul 21, 2014 5:02 pm
Question 3 was a tough one....
I had to grumble for a while
But just what i wanted to learn VHDL for.

I hope i got it correct , the RTL Viewer seems to inducate that i have.

Btw: I attacked the Logic "backwards , meaning the logic closest to the output was also written closest to the output assignment.

Does that matter ???

/Bingo

### Re: #4 Combinatorial Logic [Post Homework Here]

Posted: Tue Jul 22, 2014 3:35 pm
Bingo600 wrote:Hi Chris here is my homework for lesson4
...
...
...

All correct answers Bingo and admittedly more than I was expecting, well done! The RTL viewer is a very helpful feature as you seem to have already noticed.

Bingo600 wrote:Question 3 was a tough one....
I had to grumble for a while
But just what i wanted to learn VHDL for.

I hope i got it correct , the RTL Viewer seems to inducate that i have.

Btw: I attacked the Logic "backwards , meaning the logic closest to the output was also written closest to the output assignment.

Does that matter ???

/Bingo

Yes you answered question 3 correctly. With logic personally I tend to separate the levels out vertically and attack it input to output. But you can surely use this method from either side to build up the combinatorial logic statement.

### Re: #4 Combinatorial Logic [Post Homework Here]

Posted: Tue Jul 22, 2014 4:30 pm
ThePyroElectro wrote: With logic personally I tend to separate the levels out vertically and attack it input to output. But you can surely use this method from either side to build up the combinatorial logic statement.

So the order doesn't matter : as in

y <= d NAND ((NOT c) or (a AND b));

and

y <= ((NOT c) or (a AND b)) NAND d;

Produces the same ?

I could try ,but i'd like a definitive ansver

/Bingo

### Re: #4 Combinatorial Logic [Post Homework Here]

Posted: Tue Jul 22, 2014 4:46 pm
Bingo600 wrote:
ThePyroElectro wrote: With logic personally I tend to separate the levels out vertically and attack it input to output. But you can surely use this method from either side to build up the combinatorial logic statement.

So the order doesn't matter : as in

y <= d NAND ((NOT c) or (a AND b));

and

y <= ((NOT c) or (a AND b)) NAND d;

Produces the same ?

I could try ,but i'd like a definitive ansver

/Bingo

Hi Bingo,

I only briefly mentioned it in the video, but in this case the order of operations comes into play since we are using parenthesis, statements inside parenthesis will be given precedence and executed first.

So yes, the order won't matter. Both should work.