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Signals vs Variables

Posted: Sun Jul 13, 2014 1:58 pm
by Bingo600
Hi Chris

I was fooling a bit around and stumbled across this "Watch Out" - Signals vs variables:

http://esd.cs.ucr.edu/labs/tutorial/ind ... comb_logic
Entry : Discussion I: Signal vs. Variable:

VHDL code
http://esd.cs.ucr.edu/labs/tutorial/sig_var.vhd

Simulation
http://esd.cs.ucr.edu/labs/tutorial/sig_var.jpg
sig_var.jpg
This is the authors own simulation of what happens when the signal is not on the sensitivity list.
sig_var.jpg (41.49 KiB) Viewed 5769 times


Here he does 2 processes , one using variable and one using signal.
They have the same logic in them , but the outcome is different.


And he shows the difference in the simulation if/when you forget to put the signal in the process sensitivity list.



--------------------------------------------------------
-- Signal vs. Variable (varsig.vhd)
-- Look at the outputs in simulation waveform
-- for same computation, we get two different results
--
-- by Weijun Zhang, 05/2001
--------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity varsig is
port( d1, d2, d3: in std_logic;
res1, res2: out std_logic);
end varsig;

architecture behv of varsig is

signal sig_s1: std_logic;

begin

proc1: process(d1,d2,d3)

variable var_s1: std_logic;

begin
var_s1 := d1 and d2;
res1 <= var_s1 xor d3;
end process;


--proc2: process(d1,d2,d3) <---- sig_s1 NOT on the sensitivity list (Bad result)
proc2: process(d1,d2,d3,sig_s1) <---- sig_s1 on the sensitivity list (Good result)
begin
sig_s1 <= d1 and d2;
res2 <= sig_s1 xor d3;
end process;

end behv;


I was looking at a german forum where the "Gurus" said , that this (missing signal on the sensitivity list) would generate a warning in the synthesis tool. --- Warning German: http://www.mikrocontroller.net/topic/117630


It does under Quartus :D :

Code: Select all

Warning (10492): VHDL Process Statement warning at varsig.vhd(36): signal "sig_s1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list


But ISE says absolutely nothing to warn you :? :?

I tried to simulate it under ISE (ISIM) , but don't know how to write a testbench yet.
But i succeded in forcing d1 to be a 10ns clock , d2 to be a 20 ns clock , and d3 to be a 40 ns clock in ISIM.
And was able to generate the 2 simulation graphs:

The "bad one" where res1 & res2 are not equal , because sig_s1 is not on the slist
I wonder why my res2 below does not look like the one simulated on the edu website ???
Screenshot-ISim-sig_s1-NOT-on-slist.png
Here the signal is NOT on the sensitivity list , and the res1 & res2 simulates differently
Screenshot-ISim-sig_s1-NOT-on-slist.png (116.19 KiB) Viewed 5769 times


The "good one" where res1 & res2 are equal , because i did put sig_s1 on the slist
Screenshot-ISim-sig_s1-on-slist.png
Here the signal is on the sensitivity list , and the res1 & res2 simulates equally
Screenshot-ISim-sig_s1-on-slist.png (110.93 KiB) Viewed 5769 times



Well this was my first amateur "simulation" , and it sucks a bit.
Because if i reset it , i have to manually assign the clock to d1..3 again before they will toggle :-(

I got to learn ISIM , and get the clocks to toggle in a testbench thingy (hint..hint)

/Bingo

Re: Signals vs Variables

Posted: Sun Jul 13, 2014 5:56 pm
by ThePyroElectro
Bingo600 wrote:Hi Chris

I was fooling a bit around and stumbled across this "Watch Out" - Signals vs variables:

http://esd.cs.ucr.edu/labs/tutorial/ind ... comb_logic
Entry : Discussion I: Signal vs. Variable:

VHDL code
http://esd.cs.ucr.edu/labs/tutorial/sig_var.vhd

Simulation
http://esd.cs.ucr.edu/labs/tutorial/sig_var.jpg
sig_var.jpg


Well this was my first amateur "simulation" , and it sucks a bit.
Because if i reset it , i have to manually assign the clock to d1..3 again before they will toggle :-(

I got to learn ISIM , and get the clocks to toggle in a testbench thingy (hint..hint)

/Bingo


Well signals and variables are two very different things. I'm guessing you're studying this from a book or from the internet.
Signals are meant to route between elements inside of the CPLD/FPGA, while variables are meant simply to be used to hold values.

That's why you can't assign a variable value to a signal vector, you need to use functions to convert it over.

Since you're using the xilinx tools, getting started with ISIM is actually not too terrible. After you have your VHDL design done, you go to file->new and VHDL test bench module. Xilinx will setup all the initial parameters and in the architecture of the test bench it holds in reset for something like 50-100nS, then after that you write your stimulus VHDL code.

For some examples to get you started on that front, please see this website: http://esd.cs.ucr.edu/labs/tutorial/

Re: Signals vs Variables

Posted: Tue Jul 15, 2014 5:24 pm
by Bingo600
Chris

I was trying the examples to see if i got a warning about using a signal wo. having it on the sensitivity list.
Is the "process parameter list" called a sensisitivity list ?

I got a warning from quartus :D , but absolutely nothing from ISE :(

And also to prove by the simulation , that it would behave badly wo. the signal on the sensitivity list.
And behave correctly if i remembered to put the signal on the semsitivity list.

So it was most an "ahaaa" experience for my self , but also a bad experience that ISE didn't complain.

/Bingo