S3E Starterkit

Talk about the fifth PyroEDU course here.
Bingo600
Newbie Pyro
Posts: 75
Joined: Sat Jun 28, 2014 7:22 am

S3E Starterkit

Postby Bingo600 » Thu Jul 10, 2014 5:18 pm

Hi Chris

You got me to dig out my S3E Starterkit :D

I just loaded the demo succesfully on my Linux Mint-17

Btw: Is it ok to post all this "Non related stuff here" or should i use another sub-forum ?

/Bingo

Code: Select all

iMPACT Version: Oct 13 2013 08:43:40

iMPACT log file Started on Thu Jul 10 18:58:10 2014

Preference Table
Name                 Setting             
StartupClock         Auto_Correction     
AutoSignature        False               
KeepSVF              False               
ConcurrentMode       False               
UseHighz             False               
ConfigOnFailure      Stop               
UserLevel            Novice             
MessageLevel         Detailed           
svfUseTime           false               
SpiByteSwap          Auto_Correction     
AutoInfer            false               
SvfPlayDisplayComments false               
AutoDetecting cable. Please wait.
*** WARNING ***: When port is set to auto detect mode, cable speed is set todefault 6 MHz regardless of explicit arguments supplied for setting the baudrates
 Using windrvr6 driver.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
File version of /home/bingo/xilinx/14.7/ISE_DS/ISE/bin/lin64/xusbdfwu.hex = 1030.
File version of /usr/share/xusbdfwu.hex = 1030.
 libusb-driver.so version: 2014-06-28 19:25:04.
 Cable PID = 0008.
 Max current requested during enumeration is 74 mA.
Type = 0x0004.
 Cable Type = 3, Revision = 0.
 Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 1303.
File version of /home/bingo/xilinx/14.7/ISE_DS/ISE/data/xusb_xlp.hex = 1303.
Firmware hex file version = 1303.
PLD file version = 0012h.
 PLD version = 0012h.
Type = 0x0004.
 ESN device is not available for this cable.
'1': Loading file './s3esk_startup.bit' ...
done.
INFO:iMPACT:1777 -
   Reading /home/bingo/xilinx/14.7/ISE_DS/ISE/spartan3e/data/xc3s500e.bsd...
INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream   stored in memory,
   but the original bitstream file remains unchanged.
INFO:iMPACT:501 - '1': Added Device xc3s500e successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
INFO:iMPACT:1777 -
   Reading /home/bingo/xilinx/14.7/ISE_DS/ISE/xcf/data/xcf04s.bsd...
INFO:iMPACT:501 - '2': Added Device xcf04s successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
INFO:iMPACT:501 - '2': Added Device xcf04s successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
Warning: Chain frequency (1000000) is less than the current cable speed(6000000).
 Adjust to cable speed (1000000).
Maximum TCK operating frequency for this device chain: 1000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': IDCODE is '01000001110000100010000010010011'
'1': IDCODE is '41c22093' (in hex).
'1': : Manufacturer's ID = Xilinx xc3s500e, Version : 4
Elapsed time =      0 sec.
Maximum TCK operating frequency for this device chain: 1000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Programming device...
 LCK_cycle = NoWait.
LCK cycle: NoWait
done.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 0111 0001 1000 0000 0000 0000 0000
INFO:iMPACT:579 - '1': Completed downloading bit file to device.
INFO:iMPACT:188 - '1': Programming completed successfully.
 LCK_cycle = NoWait.
LCK cycle: NoWait
INFO:iMPACT - '1': Checking done pin....done.
'1': Programmed successfully.
Elapsed time =      5 sec.
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------

ThePyroElectro
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Posts: 1181
Joined: Mon Nov 12, 2007 9:24 pm
Location: Earth
Contact:

Re: S3E Starterkit

Postby ThePyroElectro » Thu Jul 10, 2014 7:06 pm

Bingo600 wrote:Hi Chris

You got me to dig out my S3E Starterkit :D

I just loaded the demo succesfully on my Linux Mint-17

Btw: Is it ok to post all this "Non related stuff here" or should i use another sub-forum ?

/Bingo

Code: Select all

iMPACT Version: Oct 13 2013 08:43:40

iMPACT log file Started on Thu Jul 10 18:58:10 2014


Here is fine.

The Spartan3 will have a lot more logic elements and as we went over in this week's lesson, a lot more options for different types of I/O. So once you're comfortable with the basic things like building a counter/timer/multiplexor you can go on to building more complex things, like perhaps a VGA/DVI display driver.

Bingo600
Newbie Pyro
Posts: 75
Joined: Sat Jun 28, 2014 7:22 am

Re: S3E Starterkit

Postby Bingo600 » Thu Jul 10, 2014 7:27 pm

Yipieee

My first S3E functional project , a "button" blinky.

/Bingo

Xilinx S3E Starterkit page
http://www.xilinx.com/products/boards-a ... K-US-G.htm

Userguide
http://www.xilinx.com/support/documenta ... /ug230.pdf

Schematic
http://www.xilinx.com/support/documenta ... ematic.pdf


My project well baics snipped from "hamsterwork"
http://hamsterworks.co.nz/mediawiki/ind ... PGA_course

Here
http://hamsterworks.co.nz/mediawiki/index.php/Module_2


The VHDL code

Code: Select all

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    23:48:38 07/09/2014
-- Design Name:
-- Module Name:    Switches_LEDs - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Switches_LEDs is
    Port ( switch_0 : in  STD_LOGIC;
           switch_1 : in  STD_LOGIC;
           switch_2 : in  STD_LOGIC;
           switch_3 : in  STD_LOGIC;
           btn_north : in  STD_LOGIC;
           btn_south : in  STD_LOGIC;
           btn_east : in  STD_LOGIC;
           btn_west : in  STD_LOGIC;
           led_0 : out  STD_LOGIC;
           led_1 : out  STD_LOGIC;
           led_2 : out  STD_LOGIC;
           led_3 : out  STD_LOGIC;
           led_4 : out  STD_LOGIC;
           led_5 : out  STD_LOGIC;
           led_6 : out  STD_LOGIC;
           led_7 : out  STD_LOGIC);
end Switches_LEDs;

architecture Behavioral of Switches_LEDs is

begin
   led_0 <= switch_0;
   led_1 <= switch_1;
   led_2 <= switch_2;
   led_3 <= switch_3;
   led_4 <= btn_north;
   led_5 <= btn_south;
   led_6 <= btn_east;
   led_7 <= btn_west;
end Behavioral;


The constraints file

Code: Select all

# Constraints for reference design 's3esk_startup'.
#
# Revision C of the Spartan-3E Starter Kit.
#
# Ken Chapman - Xilinx Ltd - January 2006
#                         
# Revised 16th February 2006
#
# Period constraint for 50MHz operation
#
#NET "clk" PERIOD = 20.0ns HIGH 50%;
#
# soldered 50MHz Clock.
#
#NET "clk" LOC = "C9" | IOSTANDARD = LVTTL;
#
#
# Simple LEDs
# Require only 3.5mA.
#
NET "led_0" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
NET "led_1" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
NET "led_2" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
NET "led_3" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
NET "led_4" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
NET "led_5" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
NET "led_6" LOC = "E9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
NET "led_7" LOC = "F9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
#
# Simple switches
#   Pull UP resistors used to stop floating condition during switching.
#
NET "switch_0" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP;
NET "switch_1" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP;
NET "switch_2" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP;
NET "switch_3" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP;
#
#
# Press buttons
#   Must have pull DOWN resistors to provide Low when not pressed.
#
NET "btn_north" LOC = "V4"  | IOSTANDARD = LVTTL | PULLDOWN;
NET "btn_east"  LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN;
NET "btn_south" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
NET "btn_west"  LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN;
#
# Rotary encoder.
#   Rotation contacts require pull UP resistors to provide High level.
#   Press contact requires pull DOWN resistor to provide Low when not pressed..
#
#NET "rotary_a"     LOC = "K18" | IOSTANDARD = LVTTL | PULLUP;
#NET "rotary_b"     LOC = "G18" | IOSTANDARD = LVTTL | PULLUP;
#NET "rotary_press" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN;
#
#
# LCD display
# Very slow so can use lowest drive strength.
#
#NET "lcd_rs"   LOC = "L18" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
#NET "lcd_rw"   LOC = "L17" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
#NET "lcd_e"    LOC = "M18" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
#NET "lcd_d_4" LOC = "R15" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
#NET "lcd_d_5" LOC = "R16" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
#NET "lcd_d_6" LOC = "P17" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
#NET "lcd_d_7" LOC = "M15" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
#
# Strata Flash (need to disable to use LCD display)
#
#NET "strataflash_oe" LOC = "C18" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
#NET "strataflash_ce" LOC = "D16" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
#NET "strataflash_we" LOC = "D17" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
#
#
#
# End of File
#

Bingo600
Newbie Pyro
Posts: 75
Joined: Sat Jun 28, 2014 7:22 am

Re: S3E Starterkit

Postby Bingo600 » Thu Jul 10, 2014 8:55 pm

I tried a "togle FF" on one of the pushbuttons , works but i see some "bouncing".

Had to use signal , as my led_4 <= NOT led_4 gave an error about it was "out" only and could not be read ....
Actually makes sense , could i have solved with :

led_4 : inout STD_LOGIC;


Code: Select all

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    23:48:38 07/09/2014
-- Design Name:
-- Module Name:    Switches_LEDs - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Switches_LEDs is
    Port ( switch_0 : in  STD_LOGIC;
           switch_1 : in  STD_LOGIC;
           switch_2 : in  STD_LOGIC;
           switch_3 : in  STD_LOGIC;
           btn_north : in  STD_LOGIC;
           btn_south : in  STD_LOGIC;
           btn_east : in  STD_LOGIC;
           btn_west : in  STD_LOGIC;
           led_0 : out  STD_LOGIC;
           led_1 : out  STD_LOGIC;
           led_2 : out  STD_LOGIC;
           led_3 : out  STD_LOGIC;
           led_4 : out  STD_LOGIC;
           led_5 : out  STD_LOGIC;
           led_6 : out  STD_LOGIC;
           led_7 : out  STD_LOGIC);
end Switches_LEDs;

architecture Behavioral of Switches_LEDs is
   signal state : STD_LOGIC;
begin

    process(btn_north)
    begin
        -- trig on btn_north rising edge

   --if (btn_north='1' and btn_north'event) then
   if ( RISING_EDGE(btn_north) ) then
      state <= NOT state;
   end if;

    end process;   

   led_0 <= switch_0;
   led_1 <= switch_1;
   led_2 <= switch_2;
   led_3 <= switch_3;
   led_4 <= state;
   led_5 <= btn_south;
   led_6 <= btn_east;
   led_7 <= btn_west;
end Behavioral;


And ISE 14.7 is not "happy" with my "clock/button selection"

WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component <btn_north_BUFGP/BUFG> is placed at site <BUFGMUX_X1Y0>. The IO component
<btn_north> is placed at site <IPAD171>. This will not allow the use of the fast path between the IO and the Clock
buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <btn_north.PAD>
allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that
this error condition be corrected in the design.


Had to set this in the ucf (constraint file) , to "convert the ERROR to a WARNING :?

Code: Select all

NET "btn_north" CLOCK_DEDICATED_ROUTE = FALSE;


/Bingo

Btw:

I noticed a small difference in the two if's above.
led_4 starts "0" after programming (is a signal initialized to "0" per default/starup ?)

And it seemed like if i used the "event" if' , the first push didn't turn the led on , but the 2'nd did.
And then it "toggled" fine.

If i used the RISING_EDGE if' , the the led turned on on the first keypress , and toggled fine.

This could be bouncing , and not "logic" but it was quite consistant.
Well after a few more tests , i think i was hit by bouncing

ThePyroElectro
PyroElectro Admin
Posts: 1181
Joined: Mon Nov 12, 2007 9:24 pm
Location: Earth
Contact:

Re: S3E Starterkit

Postby ThePyroElectro » Fri Jul 11, 2014 12:58 am

Bingo600 wrote:And ISE 14.7 is not "happy" with my "clock/button selection"

WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component <btn_north_BUFGP/BUFG> is placed at site <BUFGMUX_X1Y0>. The IO component
<btn_north> is placed at site <IPAD171>. This will not allow the use of the fast path between the IO and the Clock
buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <btn_north.PAD>
allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that
this error condition be corrected in the design.


Had to set this in the ucf (constraint file) , to "convert the ERROR to a WARNING :?

Code: Select all

NET "btn_north" CLOCK_DEDICATED_ROUTE = FALSE;


/Bingo

Btw:

I noticed a small difference in the two if's above.
led_4 starts "0" after programming (is a signal initialized to "0" per default/starup ?)

And it seemed like if i used the "event" if' , the first push didn't turn the led on , but the 2'nd did.
And then it "toggled" fine.

If i used the RISING_EDGE if' , the the led turned on on the first keypress , and toggled fine.

This could be bouncing , and not "logic" but it was quite consistant.
Well after a few more tests , i think i was hit by bouncing


If you don't use a GCLK or global clock input for something that appears to synthesize as a clock, ISE/Vivado will complain that you're doing something stupid and should reconsider your design. However, the override you used is the pathway to tell ISE/Vivado to do it anyway.

Later on in our course, we'll use standard data registers that include reset circuitry. The reset circuit is important because during the power-up sequence FPGAs can (and usually do...) perform a system reset. When that happens all of your signals would be initialized with whatever the reset says they should be.

There are many ways to use the clock signal in a process, in this course we'll only ever use rising_edge( ... ). The ='1' + 'event method can miss clock changes depending upon your hardware and signal flow. Here's one example - see 'practical example'.

Bingo600
Newbie Pyro
Posts: 75
Joined: Sat Jun 28, 2014 7:22 am

Re: S3E Starterkit

Postby Bingo600 » Fri Jul 11, 2014 5:30 am

ThePyroElectro wrote:There are many ways to use the clock signal in a process, in this course we'll only ever use rising_edge( ... ). The ='1' + 'event method can miss clock changes depending upon your hardware and signal flow. Here's one example - see 'practical example'.


Ahh ... This gave a nice explanation
http://vhdlguru.blogspot.com.es/2010/04 ... 4802319840


Btw: regarding me having to use a sigmal , would inout have "systhesized" ?

I mean not optimal , as it has to spend gates for being able to read the led state , but would it have been err free ?


Had to use signal , as my led_4 <= NOT led_4 gave an error about it was "out" only and could not be read ....
Actually makes sense , could i have solved with :

led_4 : inout STD_LOGIC;


/Bingo

ThePyroElectro
PyroElectro Admin
Posts: 1181
Joined: Mon Nov 12, 2007 9:24 pm
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Contact:

Re: S3E Starterkit

Postby ThePyroElectro » Fri Jul 11, 2014 9:50 pm

Bingo600 wrote:
ThePyroElectro wrote:There are many ways to use the clock signal in a process, in this course we'll only ever use rising_edge( ... ). The ='1' + 'event method can miss clock changes depending upon your hardware and signal flow. Here's one example - see 'practical example'.


Ahh ... This gave a nice explanation
http://vhdlguru.blogspot.com.es/2010/04 ... 4802319840


Btw: regarding me having to use a sigmal , would inout have "systhesized" ?

I mean not optimal , as it has to spend gates for being able to read the led state , but would it have been err free ?


Had to use signal , as my led_4 <= NOT led_4 gave an error about it was "out" only and could not be read ....
Actually makes sense , could i have solved with :

led_4 : inout STD_LOGIC;


/Bingo


Yea, that's a much more detailed explanation, with some logic analyzer photos. Glad you found it. I'm running out of time these days to make in-depth explanations like that here on the forums :(

An output signal that's listed in the top level entity cannot drive another output signal and it shouldn't. You would want to use an internal signal (std_logic) inside of the FPGA to route to and drive the output. Changing it to inout might synthesize but its possible you'll get unpredictable results because you've basically just connected the output of a 7404 hexinverter to itsself. Kind of reminds me of a ring oscillator (http://en.wikipedia.org/wiki/Ring_oscillator) :P .

While inout might seem super useful, typically I try to stay away from using it if possible because it can really over-complicate designs, unless you have a straight forward data-bus design.


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