#2 Hardware Hello World [Post Homework Here]

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ThePyroElectro
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#2 Hardware Hello World [Post Homework Here]

Postby ThePyroElectro » Thu Jul 03, 2014 6:35 pm

A new lesson was posted today:
http://www.pyroelectro.com/edu/fpga/hello_world/

Post your homework answers here to compare with everyone else!

Bingo600
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Re: #2 Hardware Hello World [Post Homework Here]

Postby Bingo600 » Thu Jul 03, 2014 7:41 pm

ThePyroElectro wrote:A new lesson was posted today:
http://www.pyroelectro.com/edu/fpga/hello_world/

Post your homework answers here to compare with everyone else!


What do you want posted ?
The whole project zipped ?
The VHDL file ?

Or ?

I hope to get my EPM240 in a few days , but have done the homework.
On my CPLD PIN_22 is used by the JTAG , so i reassigned to PIN_2

The summary says i use no logic blocks :-)


/Bingo
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ThePyroElectro
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Re: #2 Hardware Hello World [Post Homework Here]

Postby ThePyroElectro » Thu Jul 03, 2014 8:08 pm

Bingo600 wrote:What do you want posted ?
The whole project zipped ?
The VHDL file ?

Or ?

I hope to get my EPM240 in a few days , but have done the homework.
On my CPLD PIN_22 is used by the JTAG , so i reassigned to PIN_2


Hi Bingo,

This spot is for the homework questions: http://www.pyroelectro.com/edu/fpga/hello_world/homework/, they're not meant to be tough, but to cement in a few ideas that were presented in the video.

The part you're using is a little different than the EPM3032ATC44-10 we're using, so you will encounter small things here and there throughout the course like the Pin_22 to Pin_2 swap that you had to do.

Bingo600
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Re: #2 Hardware Hello World [Post Homework Here]

Postby Bingo600 » Thu Jul 03, 2014 8:40 pm

ThePyroElectro wrote:This spot is for the homework questions: http://www.pyroelectro.com/edu/fpga/hello_world/homework/, they're not meant to be tough, but to cement in a few ideas that were presented in the video.

The part you're using is a little different than the EPM3032ATC44-10 we're using, so you will encounter small things here and there throughout the course like the Pin_22 to Pin_2 swap that you had to do.


Whoopz ... embarrasing , i never went to the course page , just the forum.

I know i have ordered a different board (from UK , as i could not wait for aliexpres) , but $14 incl postage for a EPM240 were more reasonable than $10 + $17 ship. For a 3032 from the kitmakers. So i'm aware that i have to make something different.


Well back to the homework :

Why do we need a JTAG programmer in this course?

We need it for programming the CPLD with the logic file quartus generated as a result of our vhdl code.

What is the difference between an ‘entity’ and an ‘architecture’ in VHDL?

An entity defines/names the io's used in the CPLD , their name , and the type ie. input/output/clk.
An architecture defines the logic action to be taken , based on the entity pins (i hope).

Looking at the CPLD pinout, what are the 5 different types of pins on the EPM3032?

VCC,GND,CLK,IO and JTAG
Doesn't the 3032 have different Vio's for selecting voltages on i/o banks ?
Is everything in 1 i/o bank ?

I see you can choose 2.5v or 3.3v as output , is that still with 3.3v on all VCC's ?
Neat level converter

And i'll prob. have to watch out as i dont think my EPM240 is 5v tolerant as the 3032 is :?
Well i knew/expected that.


/Bingo

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Re: #2 Hardware Hello World [Post Homework Here]

Postby ThePyroElectro » Fri Jul 04, 2014 6:38 pm

Bingo600 wrote:Doesn't the 3032 have different Vio's for selecting voltages on i/o banks ?
Is everything in 1 i/o bank ?

I see you can choose 2.5v or 3.3v as output , is that still with 3.3v on all VCC's ?
Neat level converter

And i'll prob. have to watch out as i dont think my EPM240 is 5v tolerant as the 3032 is :?
Well i knew/expected that.


/Bingo


Good answers!

The EPM3032 does have two types of VCC pins. VCCINT (for internal logic power & operation) and VCCIO (for powering output signals).

The schematic as I drew it was simplified for the benefit of people who don't have much if any experience with CPLD/FPGA. But you can find the detailed pinouts for altera MAX3000A devices here: http://www.altera.com/literature/lit-dp.jsp?category=MAX%203000A

So, for +2.5v outputs you would need to set the specific VCCIO pins to +2.5v. But the VCCINT pins for MAX3000A devices still need to be +3.3v.

I don't believe that MAXII devices are +5v tolerant. There are many generic solutions to drop the voltage to tolerant levels.

Xilinx has an app-not describing their suggestions: http://www.xilinx.com/support/documentation/application_notes/xapp429.pdf

Bingo600
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Re: #2 Hardware Hello World [Post Homework Here]

Postby Bingo600 » Sat Jul 05, 2014 12:08 pm

ThePyroElectro wrote:I don't believe that MAXII devices are +5v tolerant. There are many generic solutions to drop the voltage to tolerant levels.

Xilinx has an app-not describing their suggestions: http://www.xilinx.com/support/documentation/application_notes/xapp429.pdf


I think i read thet the "2 large MAXII's" are 5v tolerant w. a 120ohm in series,
The smaller ones are not :(

Makes me wonder if they have no protection diode on their IO's

Ohh and i got my MAX240 board yesterday , and implemented lesson2.
There was allready a led on pin77 so i mapped that to LED_0 ...
I could turn on/off the led with success :D :D

There's also a 50Mhz Osc on the board , connected to clk pin12 8)
And i found a "blinky" example for the board in vhdl , it worked too :-)
It (led) was "off" every counter <= 9999999 , and "on" every counter >= 9999999 and counter <= 19999999

I had to modify it to 24999999 and 49999999 to get it to blink every sec .... It worked :-)

This is fun ......

/Bingo

Roamin
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Re: #2 Hardware Hello World [Post Homework Here]

Postby Roamin » Sat Jul 12, 2014 6:30 pm

Why do we need a JTAG programmer in this course?
To program the CPLD with the code we compiled.

What is the difference between an ‘entity’ and an ‘architecture’ in VHDL?
The entity describes the contents of our program and the architecture how different IO interact and are wired together.

Looking at the CPLD pinout, what are the 5 different types of pins on the EPM3032?
VCC, GND , IO, JTAG and Special input pins (like clocks)

ThePyroElectro
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Re: #2 Hardware Hello World [Post Homework Here]

Postby ThePyroElectro » Sun Jul 13, 2014 5:44 pm

Roamin wrote:Why do we need a JTAG programmer in this course?
To program the CPLD with the code we compiled.

What is the difference between an ‘entity’ and an ‘architecture’ in VHDL?
The entity describes the contents of our program and the architecture how different IO interact and are wired together.

Looking at the CPLD pinout, what are the 5 different types of pins on the EPM3032?
VCC, GND , IO, JTAG and Special input pins (like clocks)


Correct answers!

wingsio
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Re: #2 Hardware Hello World [Post Homework Here]

Postby wingsio » Mon Jul 24, 2017 9:59 am

Thanks for the information you brought to us. They are very interesting and new. Look forward to reading more useful and new articles from you!
wingsio


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