Search found 1172 matches

by ThePyroElectro
Thu Jul 17, 2014 8:46 pm
Forum: Introduction to CPLD and FPGA
Topic: The advanced stuff
Replies: 15
Views: 18683

Re: The advanced stuff

Bingo600 wrote:Just found this free book

http://www.freerangefactory.org/site/pm ... nloadBooks

Thought i'd share it

/Bingo


Wow, that looks like a really good book to complement this course. It details out all things about VHDL that can only be done by sitting down and reading.
by ThePyroElectro
Thu Jul 17, 2014 8:14 pm
Forum: Introduction to CPLD and FPGA
Topic: #4 Combinatorial Logic [Post Homework Here]
Replies: 7
Views: 9480

#4 Combinatorial Logic [Post Homework Here]

A new lesson was posted today:
http://www.pyroelectro.com/edu/fpga/combinatorial_logic/

Post your homework answers here to compare with everyone else!
by ThePyroElectro
Tue Jul 15, 2014 5:28 pm
Forum: Introduction to CPLD and FPGA
Topic: Altera modelsim under linux mint-17 (and ubuntu 14.04)
Replies: 1
Views: 5939

Re: Altera modelsim under linux mint-17 (and ubuntu 14.04)

While quartus installes nearly ok under linux mint-17 (just a minor challenge with web access). I had to do quite some hocuspokus , to be able to use modelsim. ... ... ... Until i started trying modelsom , QUARTUS was much easier to get running on linux , than ISE. But now i'll say they're even. No...
by ThePyroElectro
Mon Jul 14, 2014 2:53 pm
Forum: Introduction to CPLD and FPGA
Topic: #3 Input and Output [Post Homework Here]
Replies: 10
Views: 11074

Re: #3 Input and Output [Post Homework Here]

I understand that the LEDs will be brighter, I just didn't take time looking at the max 3000a datasheet to see what is the maximum current that can be sourced out of the CPLD. At 470, the LED would light with 3mA , but with 100 ohm the current would be 16mA .. a big difference , although I doubt th...
by ThePyroElectro
Sun Jul 13, 2014 6:41 pm
Forum: Projects
Topic: Question about the FM Transmitter Project
Replies: 3
Views: 4968

Re: Question about the FM Transmitter Project

Hello, I really like your FM transmitter Project and I´d like to build it by my selfe. I only have one problem: What do you mean with Toroid Core (AL=25)? Is that the inner or the outside diameter? Or is that a value for the inductance or something else? is ist possible, that you send me a link wit...
by ThePyroElectro
Sun Jul 13, 2014 6:17 pm
Forum: Introduction to CPLD and FPGA
Topic: Altera EPM240 Board
Replies: 2
Views: 5878

Re: Altera EPM240 Board

Some pretty useful links :D . We contract for the course kits with Gadgetory.com so that anyone who wants to spend the money knows exactly where to go, the cost is relatively cheap if you're just wanting to test the waters, but if you know you want to go all-in, by all means get a real board with mo...
by ThePyroElectro
Sun Jul 13, 2014 6:02 pm
Forum: Introduction to CPLD and FPGA
Topic: #3 Input and Output [Post Homework Here]
Replies: 10
Views: 11074

Re: #3 Input and Output [Post Homework Here]

How do you define a 1 bit logic input in a top level entity in VHDL? What about a 1 bit logic output? entity example is port( ENTITY_NAME: in std_logic; ENTITY_NAME2: out std_logic ); end example; *** The only thing confusing since i'm not familiar with vhdl at all is why the second entity declarat...
by ThePyroElectro
Sun Jul 13, 2014 5:56 pm
Forum: Introduction to CPLD and FPGA
Topic: Signals vs Variables
Replies: 2
Views: 6229

Re: Signals vs Variables

Hi Chris I was fooling a bit around and stumbled across this "Watch Out" - Signals vs variables: http://esd.cs.ucr.edu/labs/tutorial/index.html#comb_logic Entry : Discussion I: Signal vs. Variable: VHDL code http://esd.cs.ucr.edu/labs/tutorial/sig_var.vhd Simulation http://esd.cs.ucr.edu/...
by ThePyroElectro
Sun Jul 13, 2014 5:44 pm
Forum: Introduction to CPLD and FPGA
Topic: #2 Hardware Hello World [Post Homework Here]
Replies: 8
Views: 16738

Re: #2 Hardware Hello World [Post Homework Here]

Why do we need a JTAG programmer in this course? To program the CPLD with the code we compiled. What is the difference between an ‘entity’ and an ‘architecture’ in VHDL? The entity describes the contents of our program and the architecture how different IO interact and are wired together. Looking a...
by ThePyroElectro
Sat Jul 12, 2014 4:00 pm
Forum: Introduction to CPLD and FPGA
Topic: #3 Input and Output [Post Homework Here]
Replies: 10
Views: 11074

Re: #3 Input and Output [Post Homework Here]

Nitpicking On my S3 FPGA i can set internal PullUp/PullDown inside the IO-Block , and prob avoid the need for the external PullDown. My EE friend did advice that the button circuit oucht to draw 1..2 ma when closed , then the current flow would "burn off" the oxidation , and make the cont...
by ThePyroElectro
Sat Jul 12, 2014 3:47 pm
Forum: Introduction to CPLD and FPGA
Topic: #3 Input and Output [Post Homework Here]
Replies: 10
Views: 11074

Re: #3 Input and Output [Post Homework Here]

Hi Chris Here is my homework Btw: Did you mean "top" level" below , and were bitten by a spell checkker ? How do you define a 1 bit logic input in a topic level entity in VHDL? What about a 1 bit logic output? In the port section you define a 1 bit input as: <NAME>: in std_logic; -- ...
by ThePyroElectro
Fri Jul 11, 2014 9:50 pm
Forum: Introduction to CPLD and FPGA
Topic: S3E Starterkit
Replies: 6
Views: 7341

Re: S3E Starterkit

There are many ways to use the clock signal in a process, in this course we'll only ever use rising_edge( ... ). The ='1' + 'event method can miss clock changes depending upon your hardware and signal flow. Here's one example - see 'practical example' . Ahh ... This gave a nice explanation http://v...
by ThePyroElectro
Fri Jul 11, 2014 9:38 pm
Forum: Introduction to CPLD and FPGA
Topic: Altera Quartus Version
Replies: 9
Views: 9704

Re: Altera Quartus Version

Yea, Use the webpack 13.0SP1. Quartus II version 13.0sp1 supports all Altera University Program FPGA boards, which includes: DE0, DE0-Nano, DE1, DE2, DE2-115, DE3, DE4, and DE5-Net. Although new versions of the Quartus II software will be developed and released each year by Altera, Quartus II V13.0s...
by ThePyroElectro
Fri Jul 11, 2014 12:58 am
Forum: Introduction to CPLD and FPGA
Topic: S3E Starterkit
Replies: 6
Views: 7341

Re: S3E Starterkit

And ISE 14.7 is not "happy" with my "clock/button selection" WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component <btn_north_BUFGP/BUFG> is placed at site <BUFGMUX_X1Y0>. The IO...
by ThePyroElectro
Thu Jul 10, 2014 7:06 pm
Forum: Introduction to CPLD and FPGA
Topic: S3E Starterkit
Replies: 6
Views: 7341

Re: S3E Starterkit

Hi Chris You got me to dig out my S3E Starterkit :D I just loaded the demo succesfully on my Linux Mint-17 Btw: Is it ok to post all this "Non related stuff here" or should i use another sub-forum ? /Bingo iMPACT Version: Oct 13 2013 08:43:40 iMPACT log file Started on Thu Jul 10 18:58:10...

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