Search found 75 matches

by Bingo600
Wed Aug 13, 2014 6:56 pm
Forum: Introduction to CPLD and FPGA
Topic: S3E Lesson7
Replies: 13
Views: 24383

Re: S3E Lesson7

A bit strange .... The simulation says i'm 1 off on BCD vs SEG7 Here BCD is 1 , but SEG7 shows "0" BCD1.png Here BCD is 2 , but SEG7 shows "1" BCD2.png Here BCD is 5 , but SEG7 shows "4" BCD5.png I have activated "Reset" for 5ns at the beginning of the "S...
by Bingo600
Wed Aug 13, 2014 6:12 pm
Forum: Introduction to CPLD and FPGA
Topic: S3E Lesson7
Replies: 13
Views: 24383

Re: S3E Lesson7

I don't have the time at the moment to draw up a simulation, but if you tried to perform a test-bench for that type of process, you'd see either 'X' or 'U' outputs (undefined/unknown) during the falling edge portion of the clock. Again, that doesn't mean it won't work, just that outputs can't be gu...
by Bingo600
Tue Aug 12, 2014 8:08 pm
Forum: Introduction to CPLD and FPGA
Topic: S3E Lesson7
Replies: 13
Views: 24383

Re: S3E Lesson7

Thanx Chris

I'm toying a bit with the constraints editor , and right now it says (static timing) :

Design statistics:
Minimum period: 9.823ns{1} (Maximum frequency: 101.802MHz)


Seems like a nice constraint doc
http://www.ue.pwr.wroc.pl/pld/pld_9.pdf

/Bingo
by Bingo600
Tue Aug 12, 2014 6:09 pm
Forum: Introduction to CPLD and FPGA
Topic: S3E Lesson7
Replies: 13
Views: 24383

Re: S3E Lesson7

A thing about warnings and the FPGA tools. When you're first starting out with FPGAs its a good idea to try to understand what the warnings mean and how to mitigate them. But as you continue into FPGA, you'll see that many of the warnings are not relative to your design needs. As an example, some p...
by Bingo600
Mon Aug 11, 2014 5:21 pm
Forum: Introduction to CPLD and FPGA
Topic: #7 Parallel Hardware [Post Homework Here]
Replies: 3
Views: 10734

Re: #7 Parallel Hardware [Post Homework Here]

Hi Bingo, Correct answers! I would add two simple comments [Question 1] We can even control process flow so that they can either both be serial or parallel with other processes. Like for example if we first divide down a clock frequency with a process and then use that slower clock signal to run an...
by Bingo600
Sat Aug 09, 2014 7:58 pm
Forum: Introduction to CPLD and FPGA
Topic: The advanced stuff
Replies: 15
Views: 26073

Re: The advanced stuff

Ada 2012 Comes to ARM Cortex M3/M4
http://www.embeddedrelated.com/showarticle/617.php

How funny ......

I can almost understand it :D

No doubt where the VHDL syntax came from

/Bingo
by Bingo600
Sat Aug 09, 2014 3:06 pm
Forum: Introduction to CPLD and FPGA
Topic: S3E Lesson7
Replies: 13
Views: 24383

Re: S3E Lesson7

I did copy the ISE (S3E) VHDL to Quartus , to see if the RTL viewer was better ... It was so..so , i understand what you said in the previous lesson now. The ISE RTL is as clear as the Quartus. I have included the QII RTL & Project Ohh: And got bitten by QII , as the logic didnt fit a 32 MC CPLD...
by Bingo600
Sat Aug 09, 2014 3:03 pm
Forum: Introduction to CPLD and FPGA
Topic: S3E Lesson7
Replies: 13
Views: 24383

Re: S3E Lesson7

I got stubborn , and wanted it to be "clean" :? The : WARNING:Pack:249 - The following adjacent carry multiplexers occupy different slice components. The resulting carry chain will have suboptimal timing. Mcompar_ticks_cmp_ge0000_cy<12> Mcount_ticks_cy<0> Went away by adding a FF as prediv...
by Bingo600
Sat Aug 09, 2014 2:46 pm
Forum: Introduction to CPLD and FPGA
Topic: S3E Lesson7
Replies: 13
Views: 24383

S3E Lesson7

Chris here is my implementation on the S3E Starterboard. ISE wasn't really happy , i got two warnings WARNING:Pack:249 - The following adjacent carry multiplexers occupy different slice components. The resulting carry chain will have suboptimal timing. Mcompar_ticks_cmp_ge0000_cy<12> Mcount_ticks_cy...
by Bingo600
Sat Aug 09, 2014 12:11 pm
Forum: Introduction to CPLD and FPGA
Topic: #7 Parallel Hardware [Post Homework Here]
Replies: 3
Views: 10734

Re: #7 Parallel Hardware [Post Homework Here]

Hi Chris Here is my homework :-) What are some advantages of building CPLD hardware modules that operate in parallel? The logic flows are independant (as in per process), that makes all processes flow execute simoultainously (parallel) This capability enables us to get a FPGA/CPLD to act as if it we...
by Bingo600
Fri Aug 08, 2014 2:29 pm
Forum: Introduction to CPLD and FPGA
Topic: The advanced stuff
Replies: 15
Views: 26073

Re: The advanced stuff

Propeller Source released
http://www.parallax.com/microcontroller ... pen-source

But it seems a bit resource hungry if it can't be fully implemented on a DE0-Nano.

Wonder if a Cortex combined with a cheaper fpgaboard wouldn't be as powerfull

/Bingo
by Bingo600
Thu Aug 07, 2014 5:30 pm
Forum: Introduction to CPLD and FPGA
Topic: The advanced stuff
Replies: 15
Views: 26073

Re: The advanced stuff

CPLD VGA (Not PAL but N(ever)T(he)S(ame)C(olor) - output
http://hackaday.com/2014/08/06/thp-entr ... -and-ntsc/

Nand hacking (cool stuff)
http://hackaday.com/2014/08/06/reverse- ... algorithm/


/Bingo
by Bingo600
Wed Aug 06, 2014 1:39 pm
Forum: Introduction to CPLD and FPGA
Topic: Pin Planner problem
Replies: 2
Views: 9257

Re: Pin Planner problem

Sorry i can't help.

My crystal Ball ia a bit foggy today.
It should have shown your OS type and version. , along with the Quartus version.

/Bingo
by Bingo600
Tue Aug 05, 2014 8:38 pm
Forum: Introduction to CPLD and FPGA
Topic: FPGA's & HDMI/HD-SDI
Replies: 4
Views: 9688

Re: FPGA's & HDMI/HD-SDI

Maybe more resonable price https://www.adafruit.com/products/609 http://hackaday.com/2012/01/21/overlaying-video-on-encrypted-hdmi-connections/ Maybe Chris can try this out http://hackaday.com/2013/03/08/pumping-1080p-video-out-of-an-fpga/ And tell us beginners if it's worth beginning at http://hack...
by Bingo600
Mon Aug 04, 2014 9:23 am
Forum: Introduction to CPLD and FPGA
Topic: FPGA's & HDMI/HD-SDI
Replies: 4
Views: 9688

Re: FPGA's & HDMI/HD-SDI

You'd prob drool wildly when seeing the milkymist project (opensource) , but might be a "tad" advamced for us beginners :wink:
But lot's of "inspiration"

http://m-labs.hk/

/Bingo

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