Search found 75 matches

by Bingo600
Tue Nov 04, 2014 5:00 pm
Forum: Introduction to CPLD and FPGA
Topic: #10 VHDL vs Verilog vs Schematic [Post Homework Here]
Replies: 3
Views: 7425

Re: #10 VHDL vs Verilog vs Schematic [Post Homework Here]

Hi Chris Thank you for teking the time to overlook my ansvers , once again. The course have been "just what i neded" in order to get started with real VHDL on real hardware. And i have gotten some hands on in both the Quartus and the ISE world. If anyone else want to get their hands "...
by Bingo600
Thu Sep 04, 2014 6:26 pm
Forum: Introduction to CPLD and FPGA
Topic: #10 VHDL vs Verilog vs Schematic [Post Homework Here]
Replies: 3
Views: 7425

Re: #10 VHDL vs Verilog vs Schematic [Post Homework Here]

Chris i'm a bit late :oops: But my vacation is finish , and i was hit hard at work. Well here is my homework HOMEWORK QUESTION 1 Which design methodology (Verilog / VHDL / Schematic) is best suited for a large scale project? Why? 1: Schematic entry is cumbersome to change if large changes has to be ...
by Bingo600
Tue Aug 26, 2014 6:44 pm
Forum: Introduction to CPLD and FPGA
Topic: #9 Design a Handheld POV [Post Homework Here]
Replies: 5
Views: 7173

Re: #9 Design a Handheld POV [Post Homework Here]

HOMEWORK QUESTION 1 Modify The ROM in lesson10’s VHDL code, so the POV message will be: HELLO! I suppose you mean lesson9's .... type num_array is array (0 to 31) of std_logic_vector(7 downto 0); constant led_message : num_array := ( 0 => "00000000", -- 1 => "11111111", --******...
by Bingo600
Mon Aug 25, 2014 5:53 pm
Forum: Introduction to CPLD and FPGA
Topic: #9 Design a Handheld POV [Post Homework Here]
Replies: 5
Views: 7173

Re: #9 Design a Handheld POV [Post Homework Here]

Seems like the schematic is fixed , but not the homework

/Bingo
by Bingo600
Fri Aug 22, 2014 8:56 pm
Forum: Introduction to CPLD and FPGA
Topic: #9 Design a Handheld POV [Post Homework Here]
Replies: 5
Views: 7173

Re: #9 Design a Handheld POV [Post Homework Here]

The homework looks like the one from lesson8

/Bingo
by Bingo600
Fri Aug 22, 2014 6:26 pm
Forum: Introduction to CPLD and FPGA
Topic: The advanced stuff
Replies: 15
Views: 17027

Re: The advanced stuff

I was hunting for a "free" vhdl beautifier Either download free Sigasi (mini eclipse) w. vhdl. Or use Emacs >From here http://www.fpgarelated.com/showarticle/37.php Emacs VHDL->Beautify->Buffer Or emacs in batch mode. Linux: emacs -batch <Full path to vhdl file> -f vhdl-beautify-buffer -f ...
by Bingo600
Sun Aug 17, 2014 4:22 pm
Forum: Introduction to CPLD and FPGA
Topic: #8 LED Dimming via PWM [Post Homework Here]
Replies: 6
Views: 8536

Re: #8 LED Dimming via PWM [Post Homework Here]

Just me toying with initializers & stuff Avoiding to be bitten by "0000" fields when making the counter 5-bit long. Neat initializer stuff here http://vhdlguru.blogspot.se/2010/02/arrays-and-records-in-vhdl.html library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all...
by Bingo600
Sun Aug 17, 2014 2:39 pm
Forum: Introduction to CPLD and FPGA
Topic: #8 LED Dimming via PWM [Post Homework Here]
Replies: 6
Views: 8536

Re: #8 LED Dimming via PWM [Post Homework Here]

The fade up/down was a tough one (for me at least) I first tried with a "down" flag , that i was toggling when cnt = 100 , in the COUNTER_0 process. Then testing if it was 0 or 1 in the PWM process and "inverting the led outputs". But it was giving a pulsating output and didn't w...
by Bingo600
Sun Aug 17, 2014 2:25 pm
Forum: Introduction to CPLD and FPGA
Topic: #8 LED Dimming via PWM [Post Homework Here]
Replies: 6
Views: 8536

Re: #8 LED Dimming via PWM [Post Homework Here]

You had me on this S3E implementation :? I used the "Code" , and it was cycling much faster than your video. I thought i had an error in my 1KHz clockgenerator , and had to output 5Khz to get it to somewhat match your cycle. Then after the 3'rd watch of the video ... I noticed you count to...
by Bingo600
Sun Aug 17, 2014 2:01 pm
Forum: Introduction to CPLD and FPGA
Topic: #8 LED Dimming via PWM [Post Homework Here]
Replies: 6
Views: 8536

Re: #8 LED Dimming via PWM [Post Homework Here]

Chris here is my homework HOMEWORK QUESTION 1 Name 2 uses of PWM output signals. Driving leds Driving motors Emulating a DAC (with a LC filter on output) , i have used that for variable "contrast" on a "standard" 2x16 HD44xx char lcd. HOMEWORK QUESTION 2 What modifications would ...
by Bingo600
Sat Aug 16, 2014 6:27 pm
Forum: Introduction to CPLD and FPGA
Topic: The advanced stuff
Replies: 15
Views: 17027

Re: The advanced stuff

Just bought this Altera FPGA BaseBoard http://www.ebay.com/itm/111242540701 Mini System Development Board ALTERA FPGA CycloneII EP2C5T144 Not a bad price .... I had to get this one , where the shipping is extra. Now the Base Price is just below DK customs VAT limit (witch is $13 wo. shipping) /Bingo
by Bingo600
Wed Aug 13, 2014 8:49 pm
Forum: Introduction to CPLD and FPGA
Topic: S3E Lesson7
Replies: 13
Views: 16636

Re: S3E Lesson7

What could i have done if i still wanted the bcd-7seg process to only run on the "rising_edge" ... or bcd_value change ? It seems like when it's triggered (by only rising edge) , the bcd_value haven't changed in the other process. Could i do a : elsif rising_edge(hz_10sync) || "bcd_va...
by Bingo600
Wed Aug 13, 2014 8:31 pm
Forum: Introduction to CPLD and FPGA
Topic: S3E Lesson7
Replies: 13
Views: 16636

Re: S3E Lesson7

Well ..... I tried the assignments outside the process , it didn't help out on the 1-off SEG7 values. I had to remove the rising_edge from the BCD-7Seg process in order to get the bcd_value and the SEG7 to be in "sync" It doesn't really matter as bcd_value only changes on the "rising_...
by Bingo600
Wed Aug 13, 2014 7:24 pm
Forum: Introduction to CPLD and FPGA
Topic: S3E Lesson7
Replies: 13
Views: 16636

Re: S3E Lesson7

Hmmmm...... I think i might have the reason or ??? At the excact rising edge of hz_10sync , bcd_value hasn't incremented yet. But the value of bcd_value is used in the case ..... when assigning the SEG7 bits. Could that be the reason ? I do have bcd_value in the sensitivity list of the HC4511: proce...
by Bingo600
Wed Aug 13, 2014 7:02 pm
Forum: Introduction to CPLD and FPGA
Topic: S3E Lesson7
Replies: 13
Views: 16636

Re: S3E Lesson7

See start of sim here , where Reset is 1 for 5ns , and BCD & SEG7 are correct ... 0000 and the 7-seg value for "0" Start-Reset.png Any hints are welcome ??? Will the somulator change all signals in all proccesses immediately ? I think so , because it seems like the 1-off is lasting per...

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